Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

Press/Media: Public Engagement Activities


A video produced for IEEE Computer Society on our 2016 Journal paper, to increase uptake. This video was translated into Chinese and Spanish to increase readership.

Period28 Jul 2016

Media contributions


Media contributions

  • TitleOptimised Multiplication Architectures for Accelerating Fully homomorphic encryption
    Degree of recognitionInternational
    Media name/outletYoutube
    Media typeWeb
    Duration/Length/Size5 minutes
    CountryUnited Kingdom
    DescriptionLarge integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the
    integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a
    low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied
    to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are
    implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to
    evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up
    to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the
    proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation,
    the performance results show that a speed improvement by a factor of approximately 130 is possible.
    PersonsCiara Rafferty