• Room 03.003 - Computer Science Building

    United Kingdom

Accepting PhD Students

PhD projects

Field Programmable Gate Array High Level Synthesis Biological Signal Processing (EEG, ECG, EMG etc.) Quantum Computing Neuromorphic Computing Custom Computer Architecture

20032020

Research output per year

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Research Output

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Paper
2018

User Identification Through Wearable Antenna Characteristics at 2.45 GHz

Saadat, W., Raurale, S., Conway, G. & McAllister, J., 2018, (Accepted).

Research output: Contribution to conferencePaper

2013

High Performance Real-time Pre-Processing for Fixed-Complexity Sphere Decoder

Wu, Y., McAllister, J. & Wang, P., Dec 2013, p. 1250 - 1253. 4 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Soft-core Stream Processing on FPGA: An FFT Case Study

Wang, P., McAllister, J. & Wu, Y., May 2013, p. 2756 - 2760. 5 p.

Research output: Contribution to conferencePaper

10 Citations (Scopus)

Soft-core Stream Processor for Sliding Window Applications

Wang, P. & McAllister, J., Oct 2013, p. 213 - 218. 6 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Software defined FFT architecture for IEEE 802.11ac

Wang, P. & McAllister, J., Dec 2013, p. 1246-1249. 4 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)
2012

Automatic FPGA Synthesis of Memory Intensive C-based Kernels

Milford, M. & McAllister, J., Jul 2012, p. 136-143. 8 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Memory-centric VDF Graph Transformations for Practical FPGA Implementation

Milford, M. & McAllister, J., Oct 2012, p. 12-18. 8 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Valved Dataflow For FPGA Memory Hierarchy Synthesis

Milford, M. & McAllister, J., Mar 2012, p. 1645-1648. 4 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)
2011

A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors

Zheng, C., McAllister, J. & Wu, Y., Jul 2011, p. 278 -285. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

A Low Complexity Real-time MIMO-Preprocessing For Fixed Complexity Sphere Decoder

Chu, X., McAllister, J. & Woods, R., Nov 2011, p. 102-106. 5 p.

Research output: Contribution to conferencePaper

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

Chu, X., McAllister, J. & Woods, R., Mar 2011, p. 129-140. 12 p.

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Tree-Based Adaptive Spatial Detection for Adaptive Modulated MIMO Systems

Zheng, C., Wu, Y., McAllister, J. & Woods, R., Nov 2011, p. 107-113. 5 p.

Research output: Contribution to conferencePaper

2010

FPGA based Soft-core SIMD Processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder Case Study

Chu, X., McAllister, J. & Woods, R., Dec 2010, p. 497-484. 8 p.

Research output: Contribution to conferencePaper

13 Citations (Scopus)

Regular-Choice Petri Nets for MIMO Detectors

Zheng, C., McAllister, J. & Woods, R., Oct 2010, p. 180-185. 6 p.

Research output: Contribution to conferencePaper

2009

An Ultra-fine Processor for FPGA DSP Chip Multiprocessors

Milford, M. & McAllister, J., Nov 2009, p. 226-230. 5 p.

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Evolutionary Requirements for Next-Generation Dataflow-Based FPGA System Design

McAllister, J., Aug 2009, p. 2688-2692.

Research output: Contribution to conferencePaper

2008

Algorithmic Factorisation for Low Power FPGA Implementations Through Increased Data Locality

McKeown, M., Woods, R. & McAllister, J., Apr 2008, p. 271-274. 4 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Modified Givens Rotations and Their Application to Matrix Inversion

Ma, L., Dickson, K., McAllister, J. & McCanny, J., Mar 2008, p. 1437-1440. 4 p.

Research output: Contribution to conferencePaper

7 Citations (Scopus)
2007

SoC Memory Hierarchy Derivation from Dataflow Graphs

Fischaber, S., Woods, R. & McAllister, J., Oct 2007, p. 469-474. 6 p.

Research output: Contribution to conferencePaper

10 Citations (Scopus)
2006

Muir Hardware Synthesis for Multimedia Applications

Fischaber, S., McAllister, J., Woods, R. & Malins, E., Nov 2006, p. 1-13. 13 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)
2005

FPGA Core Network Implementation and Optimization: A Case Study

Fischaber, S., Hasson, R., McAllister, J. & Woods, R., Dec 2005, p. 319-320. 2 p.

Research output: Contribution to conferencePaper

Rapid Generation of Hardware Functionality in Heterogeneous Platforms

Reilly, D., Woods, R., McAllister, J. & Walke, R., Mar 2005, p. V65-V68. 4 p.

Research output: Contribution to conferencePaper

2004

Embedded Context Aware Hardware Component Generation for Dataflow System Exploration

McAllister, J., Woods, R. & Walke, R., Jul 2004, p. 254-263. 10 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Synthesis and High Level Optimisation of Multidimensional Dataflow Actor Network on FPGA

McAllister, J., Woods, R., Walke, R. & Reilly, D., Sep 2004, p. 164-169. 6 p.

Research output: Contribution to conferencePaper

9 Citations (Scopus)
2003

Design Technologies for DSP Algorithm Implementation on Heterogeneous Architectures

McAllister, J., Yi, Y., Woods, R., Walke, R., Reilly, D. & Colgan, K., Aug 2003, p. 585-596. 12 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)