Roger Woods

Research output

Research output per year 1988 1998 2000 2001 2005 2007 2008 2010 2011 2014 2017 2018 2019 2022

• 79 Paper
• 71 Article
• 54 Conference contribution
• 8 Book
• 20 More
  • 5 Chapter
  • 5 Editorial
  • 2 Other chapter contribution
  • 2 Poster
  • 1 Commissioned report
  • 1 Foreword/postscript
  • 1 Chapter (peer-reviewed)
  • 1 Abstract
  • 1 Comment/debate
  • 1 Patent

Research output per year

Research output per year

Search results

• 2009

  Replacing Uncertainty Decoding with Subband Re-Estimation for Large Vocabulary

  Lu, J., Ji, M. & Woods, R., Sep 2009, p. 2407-2410. 4 p.

  Research output: Contribution to conference › Paper

  2 Citations (Scopus)

• SoC memory hierarchy derivation from dataflow graphs

  Fischaber, S., Woods, R. & McAllister, J., Sep 2009, In: Journal of Signal Processing Systems. 60, 3, p. 345-361 17 p.

  Research output: Contribution to journal › Article › peer-review

  • System-on-chip 100%
  • Data Flow 69%
  • Data storage equipment 31%
  • Chip 28%
  • Motion Estimation 24%
  3 Citations (Scopus)

  3 Downloads (Pure)
• 2008

  A Distributed Network Monitor for Flow Detection and Classification

  McGlone, J., Marshall, A. & Woods, R., Apr 2008, p. 871-874. 4 p.

  Research output: Contribution to conference › Paper

  1 Citation (Scopus)

• Algorithmic Factorisation for Low Power FPGA Implementations Through Increased Data Locality

  McKeown, M., Woods, R. & McAllister, J., Apr 2008, p. 271-274. 4 p.

  Research output: Contribution to conference › Paper › peer-review
  5 Citations (Scopus)

• A real-time flow monitor architecture encompassing on-demand monitoring functions

  McGlone, J., Marshall, A. & Woods, R., Apr 2008, p. 871-874. 4 p.

  Research output: Contribution to conference › Paper

  1 Citation (Scopus)

• Combining noise compensation and missing-feature decoding for large vocabulary speech recognition in noise

  Lu, J., Ji, M. & Woods, R., Sep 2008, p. 1269-1272. 4 p.

  Research output: Contribution to conference › Paper

• Design methodology for a block motion estimation IP core

  Turner, R. H., Woods, R., Fischaber, S. & McAllister, J., 22 Sep 2008, 2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP. p. 711-716 6 p. 4590443. (2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Intellectual property core 100%
  • Image compression 39%
  • Data storage equipment 23%
  • Industry 17%

• From bit level systolic arrays to HDTV processor chips

  Woods, R. F., McCanny, J. V. & McWhirter, J. G., 01 Nov 2008, In: Journal of Signal Processing Systems. 53, 1-2 SPEC. ISS., p. 35-49 15 p.

  Research output: Contribution to journal › Article › peer-review

  • Systolic Array 100%
  • Chip 88%
  • System-on-chip 80%
  • Design 43%
  • Impulse Response 32%
  2 Citations (Scopus)

• Lecture Notes in Computer Science: Preface

  Woods, R., Compton, K., Bouganis, C. & Diniz, P. C., 22 Sep 2008, In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4943 LNCS

  Research output: Contribution to journal › Editorial › peer-review

• Memory-Centric Hardware Synthesis from Dataflow Models

  Fischaber, S., McAllister, J. & Woods, R. (ed.), Jul 2008, Embedded Computer Systems: Architectures, Modeling, and Simulation. p. 197-206 10 p. (Lecture Notes in Computer Science; vol. 5114).

  Research output: Chapter in Book/Report/Conference proceeding › Chapter

  • Data storage equipment 100%
  • Computer hardware 96%
  • Intellectual property core 41%
  • Template matching 38%
  • Computer simulation 17%
  1 Citation (Scopus)

• Novel percussive instrument design - Converting mathematical formulae into engaging musical instruments

  Chuchacz, K., Woods, R. & O'Modhrain, S., 01 Jan 2008.

  Research output: Contribution to conference › Paper › peer-review

  • Musical instruments 100%
  • Hardware 40%
  • Timpani 32%
  • Performer 31%
  • Expressive Performance 27%

• Power Efficient DSP Datapath Configuration Methodology for FPGA

  McKeown, M., Woods, R. & McAllister, J., Sep 2008, 2008 International Conference on Field Programmable Logic and Applications. Proceedings. p. 515-518 4 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Intellectual property core 77%
  2 Citations (Scopus)

• Power Efficient Dynamic-Range Utilisation for DSP On FPGA

  McKeown, M., Woods, R. & McAllister, J., Oct 2008, 2008 IEEE Workshop on Signal Processing Systems. p. 233-238 6 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Intellectual property core 100%
  • Electric power utilization 38%
  • Data streams 26%
  • Fast Fourier transforms 25%
  • Redundancy 22%
  1 Citation (Scopus)

• QR Recursive Least Squares IP Core Example

  Lightbody, G. & Woods, R., Mar 2008, p. 369-374. 6 p.

  Research output: Contribution to conference › Paper

  1 Citation (Scopus)

• Reconfigurable Computing: Architectures, Tools and Applications

  Woods, R., Compton, K., Bouganis, C. & Diniz, P., Mar 2008, Springer. 344 p.

  Research output: Book/Report › Book

• Robustness in digital hardware

  Woods, R. & Lightbody, G., 01 Dec 2008, Robust Intelligent Systems. Springer London, p. 3-21 19 p.

  Research output: Chapter in Book/Report/Conference proceeding › Chapter

  • Computer hardware 100%
  • Banking 65%
  • Entertainment 61%
  • Electronic equipment 48%
  • Communication systems 45%
  1 Citation (Scopus)

• Towards a real-time implementation of a physical modeling based percussion synthesizer

  Chuchacz, K., Woods, R. & O'Modhrain, S., 01 Dec 2008, Audio Engineering Society - 124th Audio Engineering Society Convention 2008. Vol. 2. p. 692-697 6 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • percussion 100%
  • Physical Modeling 97%
  • Real-time 73%
  • Field Programmable Gate Array 51%
  • Hardware Implementation 49%
  2 Citations (Scopus)

• Towards a real-time implementation of a physical modelling based percussion synthesizer

  Chuchcaz, K., Woods, R. & O'Modhrain, S., May 2008, p. 1-1. 1 p.

  Research output: Contribution to conference › Paper
• 2007

  DESIGN METHODOLOGY FOR A BLOCK MOTION ESTIMATION IP CORE

  Turner, R., Woods, R., Fischaber, S. & McAllister, J., Jun 2007, p. 711-716. 6 p.

  Research output: Contribution to conference › Paper

• Design Methodology for Real-Time FPGA-Based Sound Synthesis

  Motuk, E., Woods, R., Bilbao, S. & McAllister, J., Dec 2007, In: IEEE Transactions on Signal Processing. 55(12), 12, p. 5833-5845 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Musical instruments 100%
  • Membranes 29%
  • Acoustic waves 27%
  • Boundary conditions 27%
  11 Citations (Scopus)

• Editorial: Transforming signal processing applications into parallel implementations

  Deprettre, E. F., Woods, R., Verbauwhede, I. & De Kock, E., 23 Nov 2007, In: EURASIP Journal on Advances in Signal Processing. 2007, 95760.

  Research output: Contribution to journal › Editorial › peer-review

• Physical models and musical controllers: Designing a novel electronic percussion instrument

  Chuchacz, K., O'Modhrain, S. & Woods, R., 01 Dec 2007, p. 37-40. 4 p.

  Research output: Contribution to conference › Paper › peer-review

  • Acoustic waves 100%
  • Controllers 68%
  9 Citations (Scopus)

• Programmable network functionality for improved QoS of interactive video traffic

  McAllister, B., Marshall, A. & Woods, R., Nov 2007, p. 283-296. 14 p.

  Research output: Contribution to conference › Paper

• Programmable SoC processor for video object recognition and tracking applications

  Kurnarasamy, M., Woods, R. & Miller, P., Nov 2007, p. 2004-2008. 5 p.

  Research output: Contribution to conference › Paper

  1 Citation (Scopus)

• Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

  McAllister, J., Woods, R., Fischaber, S. & Malins, E., Aug 2007, In: Journal of Systems Architecture. 53 (8), 8, p. 511-523 13 p.

  Research output: Contribution to journal › Article › peer-review

  • Signal processing 98%
  • Sonar 68%
  • Computer systems 53%
  • Radar 49%
  • Communication 30%
  9 Citations (Scopus)

• SoC Memory Hierarchy Derivation from Dataflow Graphs

  Fischaber, S., Woods, R. & McAllister, J., Oct 2007, p. 469-474. 6 p.

  Research output: Contribution to conference › Paper › peer-review

  10 Citations (Scopus)

• Soft IP core implementation of recursive least squares filter using only multplicative and additive operators

  Lightbody, G., Woods, R. & Francey, J., 01 Dec 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 597-600 4 p. 4380725

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Intellectual property core 100%
  • Networks (circuits) 14%
  4 Citations (Scopus)
• 2006

  From bit level systolic arrays to HDTV processor chips

  McCanny, J. V., Woods, R. F. & McWhirter, J. G., 01 Jan 2006, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. p. 159-162 4 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • High definition television 98%
  • Signal processing 62%

• Hierarchical Synthesis of Complex DSP Functions Using IRIS

  Woods, R. & Yi, Y., May 2006, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(5), 5, p. 806-820 15 p.

  Research output: Contribution to journal › Article › peer-review
  7 Citations (Scopus)

• Improving the delivery of Interactive Video over QoS enabled IP Networks

  McAllister, B., Marshall, A. & Woods, R., May 2006.

  Research output: Contribution to conference › Paper

• Muir Hardware Synthesis for Multimedia Applications

  Fischaber, S., McAllister, J., Woods, R. & Malins, E., Nov 2006, p. 1-13. 13 p.

  Research output: Contribution to conference › Paper › peer-review

  1 Citation (Scopus)

• Multidimensional DSP Core Synthesis for FPGA

  McAllister, J., Woods, R., Walke, R. & Reilly, D., Jun 2006, In: Journal of VLSI signal processing systems for signal, image and video technology. 43(2-3), 2-3, p. 207-221 15 p.

  Research output: Contribution to journal › Article › peer-review

  • Computer systems 100%
  • Sonar 64%
  • Signal processing 45%
  • Radar 45%
  • Systems analysis 42%
  12 Citations (Scopus)

• Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch

  O'Neill, S., Marshall, A. & Woods, R., Jun 2006, p. 725-730. 6 p.

  Research output: Contribution to conference › Paper
• 2005

  A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services Network

  O'Neill, S., Marshall, A. & Woods, R., 2005, NETWORKING 2005. Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communications Systems. Springer, p. 1031-1042 12 p. (Lecture Notes in Computer Science; vol. 3462).

  Research output: Chapter in Book/Report/Conference proceeding › Chapter

  • Packet loss 100%
  • Quality of service 78%
  • Internet 68%
  • Bandwidth 62%
  1 Citation (Scopus)

• Dataflow-based design methodology for DSP SoC systems

  Woods, R., 25 Aug 2005, Proceedings of the 2005 IEEE International Workshop on VLSI Design and Video Technology, IWVDVT 2005. 1 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Intellectual property core 100%
  • System-on-chip 80%
  • Silicon 46%
  • Cryptography 16%
  • Availability 13%

• FPGA-based hardware for physical modelling sound synthesis by finite difference schemes

  Motuk, E., Woods, R. & Bilbao, S., Dec 2005, p. 103-110. 8 p.

  Research output: Contribution to conference › Paper

  8 Citations (Scopus)

• FPGA-based physical modeling hardware for musical sound synthesis

  Motuk, E., Woods, R. & Dr, S. B., Dec 2005, p. 103-110. 8 p.

  Research output: Contribution to conference › Paper

• FPGA Core Network Implementation and Optimization: A Case Study

  Fischaber, S., Hasson, R., McAllister, J. & Woods, R., Dec 2005, p. 319-320. 2 p.

  Research output: Contribution to conference › Paper › peer-review

• Guest Editorial: Cryptography algorithms and architectures for System-on-Chip

  Gocan, S., O'Neill, M., Paar, C. & Woods, R., 2005, In: IEE Proc. on Information Security. 1, p. 1-2 2 p.

  Research output: Contribution to journal › Article › peer-review

• High Speed FPGA-based implementations of Delayed-LMS filters

  Ting, L. K., Woods, R. & Cowan, C., Jan 2005, In: Journal of VLSI Signal Processing. 39, 1-2 SPEC.ISS., p. 113-131 19 p.

  Research output: Contribution to journal › Article › peer-review

  • Networks (circuits) 67%
  • Adaptive filters 66%
  • Digital filters 65%
  • Computer hardware 35%
  46 Citations (Scopus)

• Implementation of finite difference schemes for the wave equation on FPGA

  Motuk, E., Woods, R. & Bilbao, S., Mar 2005, p. III237-III240. 4 p.

  Research output: Contribution to conference › Paper

  17 Citations (Scopus)

• Novel Network Functionality for Interactive layered MPEG-4 Video Conferencing

  McAllister, B., Marshall, A. & Woods, R., Mar 2005, p. 61-62. 2 p.

  Research output: Contribution to conference › Paper

• Parallel implementation of finite difference schemes for the plate equation on a FPGA-based multi-processor array

  Motuk, E., Woods, R. & Bilbao, S., 01 Dec 2005, 13th European Signal Processing Conference, EUSIPCO 2005. p. 1846-1849 4 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  1 Citation (Scopus)

• Programmable Network Functionality for Improved QoS of Interactive Video Traffic

  McAllister, B., Marshall, A. & Woods, R., Nov 2005.

  Research output: Contribution to conference › Paper

• Rapid Generation of Hardware Functionality in Heterogeneous Platforms

  Reilly, D., Woods, R., McAllister, J. & Walke, R., Mar 2005, p. V65-V68. 4 p.

  Research output: Contribution to conference › Paper › peer-review

• Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

  McAllister, J., Woods, R., Reilly, D., Fischaber, S. & Hasson, R., Jul 2005, Embedded Computer Systems: Architectures, Modelling and Simulation. Hamalainen, T., Pimentel, A., Takala, J. & Vassiliadis, S. (eds.). Springer, p. 414-423 10 p. (Lecture Notes In Computer Science; vol. 3553).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Logic devices 100%
  • Digital signal processing 79%
  • Computer hardware 45%

• Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

  Woods, R., Cowan, C. & Ting, L. K., Jan 2005, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13 (1), 1, p. 86-95 10 p.

  Research output: Contribution to journal › Article › peer-review

  • Pipelines 31%
  • Sampling 28%
  66 Citations (Scopus)
• 2004

  Clear future direction

  Woods, R., 2004, In: IEE Review. 50, p. 56-56 1 p.

  Research output: Contribution to journal › Article › peer-review

• Embedded Context Aware Hardware Component Generation for Dataflow System Exploration

  McAllister, J., Woods, R. & Walke, R., Jul 2004, p. 254-263. 10 p.

  Research output: Contribution to conference › Paper › peer-review

  1 Citation (Scopus)

• Guest Editorial: Field Programmable Logic

  Woods, R. & Professor, R. T., Jan 2004, In: Journal of VLSI Signal Processing. 36 (1), 1, p. 5-6 2 p.

  Research output: Contribution to journal › Article › peer-review