64-point Fourier transform chip for digital television applications

John V. McCanny, Roger F. Woods, Colin Hui, Tiong Jui Ding, Bruce Devlin, Andrew Major

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.
Original languageEnglish
Pages (from-to)250-251
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 01 Feb 1996

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.


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