64-point Fourier transform chip for digital television applications

John V. McCanny; Roger F. Woods; Colin Hui; Tiong Jui Ding; Bruce Devlin; Andrew Major

64-point Fourier transform chip for digital television applications

John V. McCanny, Roger F. Woods, Colin Hui, Tiong Jui Ding, Bruce Devlin, Andrew Major

Research output: Contribution to journal › Article › peer-review

Abstract

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

Original language	English
Pages (from-to)	250-251
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	39
Publication status	Published - 01 Feb 1996

Bibliographical note

Cite this

@article{2d33e85761a54fb7bdba07d8cfe6afe1,

title = "64-point Fourier transform chip for digital television applications",

abstract = "A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.",

author = "McCanny, {John V.} and Woods, {Roger F.} and Colin Hui and Ding, {Tiong Jui} and Bruce Devlin and Andrew Major",

year = "1996",

month = feb,

day = "1",

language = "English",

volume = "39",

pages = "250--251",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - 64-point Fourier transform chip for digital television applications

AU - McCanny, John V.

AU - Woods, Roger F.

AU - Hui, Colin

AU - Ding, Tiong Jui

AU - Devlin, Bruce

AU - Major, Andrew

PY - 1996/2/1

Y1 - 1996/2/1

N2 - A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

AB - A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

UR - http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-0030087142&md5=e727cd13fa7c7e63488e80dabc328244

M3 - Article

AN - SCOPUS:0030087142

VL - 39

SP - 250

EP - 251

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

ER -

64-point Fourier transform chip for digital television applications

Abstract

Bibliographical note

Other files and links

Fingerprint

Cite this