A 40 megasample IIR filter chip

J. V. McCanny, R. F. Woods

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The design of a high performance bit parallel second order IIR filter chip is described. The chip in question is highly pipelined, uses most significant bit first arithmetic and consists mainly of arrays of simple carry save adders. It has been fabricated in 1.5 um double level metal CMOS technology, accepts 12 bit input data and coefficient values and can operate at up to 40 megasamples per second. All data inputs and outputs are in two's complement form, and the chip power consumption is 1W. The highly regular nature of the architecture has been exploited for test pattern generation. It is shown how small, but important modifications to the basic architecture, can significantly improve testing. As a result, 100% fault coverage can be achieved using less than 1000 test vectors. The chip may be used in a cascade realisation to form a general nth order filter.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Application Specific Array Processors, ASAP 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages416-430
Number of pages15
ISBN (Electronic)0818692375, 9780818692376
DOIs
Publication statusPublished - 01 Jan 1991
Externally publishedYes
Event1991 International Conference on Application Specific Array Processors, ASAP 1991 - Barcelona, Spain
Duration: 02 Sep 199104 Sep 1991

Conference

Conference1991 International Conference on Application Specific Array Processors, ASAP 1991
CountrySpain
CityBarcelona
Period02/09/199104/09/1991

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Control and Systems Engineering

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