A 5-GHz Class-E3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS

Matthew Love; Mury Thian; Andrei Grebennikov

doi:10.1109/WAMICON.2017.7930264

A 5-GHz Class-E3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS

Matthew Love
, Mury Thian
, Andrei Grebennikov

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

765 Downloads (Pure)

Abstract

The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and -F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 51% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to -47.6 dBc and -79.3 dBc, respectively.

Original language	English
Title of host publication	Proceedings of the 2017 IEEE Wireless and Microwave Technology Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	4
ISBN (Electronic)	978-1-5090-4375-0, 978-1-5090-4374-3
ISBN (Print)	978-1-5090-4376-7
DOIs	https://doi.org/10.1109/WAMICON.2017.7930264
Publication status	Published - 18 May 2017
Event	IEEE Wireless and Microwave Technology Conference - Florida, United States Duration: 24 Apr 2017 → 25 Apr 2017

Conference

Conference	IEEE Wireless and Microwave Technology Conference
Abbreviated title	WAMICON
Country/Territory	United States
City	Florida
Period	24/04/2017 → 25/04/2017

Access to Document

10.1109/WAMICON.2017.7930264Licence: Unspecified

A 5-GHz Class-E3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS
© 2017 IEEE. This work is made available online in accordance with the publisher’s policies. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 531 KBLicence: Unspecified

Best Student Paper Award at IEEE WAMICON 2017
Love, M. (Recipient), Thian, M. (Recipient) & Grebennikov, A. (Recipient), 24 Apr 2017
Prize: Prize (including medals and awards)

Cite this

@inproceedings{592753b4ce094788a45a0d40d2d67b15,

title = "A 5-GHz Class-E3F2 Power Amplifier with 51\% PAE and 21-dBm Output Power on 65nm CMOS",

abstract = "The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and -F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 51\% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to -47.6 dBc and -79.3 dBc, respectively.",

author = "Matthew Love and Mury Thian and Andrei Grebennikov",

year = "2017",

month = may,

day = "18",

doi = "10.1109/WAMICON.2017.7930264",

language = "English",

isbn = "978-1-5090-4376-7",

booktitle = "Proceedings of the 2017 IEEE Wireless and Microwave Technology Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE Wireless and Microwave Technology Conference, WAMICON ; Conference date: 24-04-2017 Through 25-04-2017",

}

Love, M, Thian, M & Grebennikov, A 2017, A 5-GHz Class-E3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS. in Proceedings of the 2017 IEEE Wireless and Microwave Technology Conference. Institute of Electrical and Electronics Engineers Inc., IEEE Wireless and Microwave Technology Conference, Florida, United States, 24/04/2017. https://doi.org/10.1109/WAMICON.2017.7930264

TY - GEN

T1 - A 5-GHz Class-E3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS

AU - Love, Matthew

AU - Thian, Mury

AU - Grebennikov, Andrei

PY - 2017/5/18

Y1 - 2017/5/18

N2 - The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and -F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 51% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to -47.6 dBc and -79.3 dBc, respectively.

AB - The design and simulation of a Class-E3F2 power amplifier using 65nm CMOS technology are detailed in this paper. The Class-EF amplifier combines aspects of the Class-E and -F load networks such as the harmonic terminations from the Class F and the use of a shunt capacitance at the drain in the Class E. A mixed-voltage cascode topology is used for the output stage to enable the use of fast low-voltage transistors with a higher supply voltage. To satisfy the Class-EF conditions the load network is designed to provide a short and open circuit to the second and third harmonic signals, respectively. The driver stage utilizes an Inverse Class-B topology to deliver a half-wave rectified sine to the output stage. The simulated amplifier achieved a power-added efficiency of 51% and a gain of 26 dB at an output power of 21 dBm. The second and third harmonic components were attenuated to -47.6 dBc and -79.3 dBc, respectively.

U2 - 10.1109/WAMICON.2017.7930264

DO - 10.1109/WAMICON.2017.7930264

M3 - Conference contribution

SN - 978-1-5090-4376-7

BT - Proceedings of the 2017 IEEE Wireless and Microwave Technology Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Wireless and Microwave Technology Conference

Y2 - 24 April 2017 through 25 April 2017

ER -

A 5-GHz Class-E3F2 Power Amplifier with 51% PAE and 21-dBm Output Power on 65nm CMOS

Abstract

Conference

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Prizes

Best Student Paper Award at IEEE WAMICON 2017

Cite this