A 5.6-GHz Class-DE power amplifier with reduced voltage stress in 22-nm FDSOI CMOS

Matthew Love*, Mury Thian*, Floris van der Wilt, Koen van Hartingsveldt, Kave Kianush

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
372 Downloads (Pure)

Abstract

This paper presents a 5.6 GHz Class-DE power amplifier (PA) with reduced voltage stress compared to classical PA designs. CMOS PAs are susceptible to a number of breakdown phenomena such as drain oxide breakdown and hot-carrier injection (HCI) which can significantly reduce their lifespan. The Class-DE amplifier is a hard-switching device which minimizes voltage-current overlap across the channel which significantly reduces the risk of HCI effects. The PA does not use an RF choke which limits the peak drain voltage to V DD , limiting the risk of drain oxide breakdown. The driver circuit gives a duty cycle below 50% and ensures that each transistor is almost completely off before the other has turned on. The PA achieves 47.9% power-added efficiency, 22.2 dBm output power, and 28.2 dB gain with a single 2.2 V supply voltage. Transient simulations of the PA's drain currents and voltages confirm the low current-voltage overlap which shows that the PA has much less risk of HCI effects than classical PA designs.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Microwave Conference (APMC) 2019: Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages470-472
Number of pages3
ISBN (Electronic)9781728135175
ISBN (Print)9781728135182
DOIs
Publication statusPublished - 19 Mar 2020

Publication series

NameIEEE Asia-Pacific Microwave Conference (APMC) Proceedings
PublisherIEEE
ISSN (Electronic)2690-3946

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