Abstract
This paper presents a 5.6 GHz Class-DE power amplifier (PA) with reduced voltage stress compared to classical PA designs. CMOS PAs are susceptible to a number of breakdown phenomena such as drain oxide breakdown and hot-carrier injection (HCI) which can significantly reduce their lifespan. The Class-DE amplifier is a hard-switching device which minimizes voltage-current overlap across the channel which significantly reduces the risk of HCI effects. The PA does not use an RF choke which limits the peak drain voltage to V DD , limiting the risk of drain oxide breakdown. The driver circuit gives a duty cycle below 50% and ensures that each transistor is almost completely off before the other has turned on. The PA achieves 47.9% power-added efficiency, 22.2 dBm output power, and 28.2 dB gain with a single 2.2 V supply voltage. Transient simulations of the PA's drain currents and voltages confirm the low current-voltage overlap which shows that the PA has much less risk of HCI effects than classical PA designs.
Original language | English |
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Title of host publication | IEEE Asia-Pacific Microwave Conference (APMC) 2019: Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 470-472 |
Number of pages | 3 |
ISBN (Electronic) | 9781728135175 |
ISBN (Print) | 9781728135182 |
DOIs | |
Publication status | Published - 19 Mar 2020 |
Publication series
Name | IEEE Asia-Pacific Microwave Conference (APMC) Proceedings |
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Publisher | IEEE |
ISSN (Electronic) | 2690-3946 |
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Dive into the research topics of 'A 5.6-GHz Class-DE power amplifier with reduced voltage stress in 22-nm FDSOI CMOS'. Together they form a unique fingerprint.Student theses
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Efficiency improvement in nanometre CMOS outphasing power amplifiers
Love, M. (Author), Buchanan, N. (Supervisor) & Zelenchuk, D. (Supervisor), Jul 2021Student thesis: Doctoral Thesis › Doctor of Philosophy
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