A bit-level systolic architecture for implementing a VQ tree search

M. Yan, J.V. McCanny

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system.
Original languageEnglish
Pages (from-to)149-158
Number of pages10
JournalJournal of VLSI signal processing systems for signal, image and video technology
Issue number3
Publication statusPublished - 01 Nov 1990

Bibliographical note

Copyright 2007 Elsevier B.V., All rights reserved.


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