A compressed and accurate sparse deep learning-based workload-aware timing error model

Styliani Tompazi; Georgios Karakonstantis

doi:10.1109/ICCD58817.2023.00012

A compressed and accurate sparse deep learning-based workload-aware timing error model

Styliani Tompazi^*
, Georgios Karakonstantis

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper showcases the novel application of Deep-Learning (DL) in the development of accurate microarchitecture and workload-aware timing error models and investigates methods such as sparsification for reducing their complexity, while maintaining high accuracy. Our study shows that DL can help increase the accuracy and true positive rate (TPR) of workload-aware models for a pipelined floating-point core compared to existing models. In addition, we demonstrate that removing up to 40% of the total neurons has minimal impact on the accuracy and overall predictive performance (up to 2.2%) of our DL-based timing error models, while significantly reducing the computational complexity. In fact, the complexity of the sparse model is approximately 2× smaller than the dense one.

Original language	English
Title of host publication	Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	9-12
Number of pages	4
ISBN (Electronic)	9798350342918
ISBN (Print)	9798350342925
DOIs	https://doi.org/10.1109/ICCD58817.2023.00012
Publication status	Published - 22 Dec 2023
Event	41st IEEE International Conference on Computer Design 2023 - Washington, United States Duration: 06 Nov 2023 → 08 Nov 2023

Publication series

Name	International Conference on Computer Design (ICCD) Proceedings
ISSN (Print)	1063-6404
ISSN (Electronic)	2576-6996

Conference

Conference	41st IEEE International Conference on Computer Design 2023
Abbreviated title	ICCD 2023
Country/Territory	United States
City	Washington
Period	06/11/2023 → 08/11/2023

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD58817.2023.00012Licence: Unspecified

Microarchitecture and workload-aware error prediction based on artificial intelligence
Tompazi, S. (Author), Karakonstantis, G. (Supervisor) & Martinez del Rincon, J. (Supervisor), Jul 2025
Student thesis: Doctoral Thesis › Doctor of Philosophy

File

Cite this

Tompazi, S., & Karakonstantis, G. (2023). A compressed and accurate sparse deep learning-based workload-aware timing error model. In Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023 (pp. 9-12). (International Conference on Computer Design (ICCD) Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD58817.2023.00012

@inproceedings{3182f8d9d6504be8868e10832a777212,

title = "A compressed and accurate sparse deep learning-based workload-aware timing error model",

abstract = "This paper showcases the novel application of Deep-Learning (DL) in the development of accurate microarchitecture and workload-aware timing error models and investigates methods such as sparsification for reducing their complexity, while maintaining high accuracy. Our study shows that DL can help increase the accuracy and true positive rate (TPR) of workload-aware models for a pipelined floating-point core compared to existing models. In addition, we demonstrate that removing up to 40\% of the total neurons has minimal impact on the accuracy and overall predictive performance (up to 2.2\%) of our DL-based timing error models, while significantly reducing the computational complexity. In fact, the complexity of the sparse model is approximately 2× smaller than the dense one. ",

author = "Styliani Tompazi and Georgios Karakonstantis",

year = "2023",

month = dec,

day = "22",

doi = "10.1109/ICCD58817.2023.00012",

language = "English",

isbn = "9798350342925",

series = "International Conference on Computer Design (ICCD) Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "9--12",

booktitle = "Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023",

address = "United States",

note = "41st IEEE International Conference on Computer Design 2023, ICCD 2023 ; Conference date: 06-11-2023 Through 08-11-2023",

}

Tompazi, S & Karakonstantis, G 2023, A compressed and accurate sparse deep learning-based workload-aware timing error model. in Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023. International Conference on Computer Design (ICCD) Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 9-12, 41st IEEE International Conference on Computer Design 2023, Washington, United States, 06/11/2023. https://doi.org/10.1109/ICCD58817.2023.00012

A compressed and accurate sparse deep learning-based workload-aware timing error model. / Tompazi, Styliani; Karakonstantis, Georgios.
Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 9-12 (International Conference on Computer Design (ICCD) Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A compressed and accurate sparse deep learning-based workload-aware timing error model

AU - Tompazi, Styliani

AU - Karakonstantis, Georgios

PY - 2023/12/22

Y1 - 2023/12/22

N2 - This paper showcases the novel application of Deep-Learning (DL) in the development of accurate microarchitecture and workload-aware timing error models and investigates methods such as sparsification for reducing their complexity, while maintaining high accuracy. Our study shows that DL can help increase the accuracy and true positive rate (TPR) of workload-aware models for a pipelined floating-point core compared to existing models. In addition, we demonstrate that removing up to 40% of the total neurons has minimal impact on the accuracy and overall predictive performance (up to 2.2%) of our DL-based timing error models, while significantly reducing the computational complexity. In fact, the complexity of the sparse model is approximately 2× smaller than the dense one.

AB - This paper showcases the novel application of Deep-Learning (DL) in the development of accurate microarchitecture and workload-aware timing error models and investigates methods such as sparsification for reducing their complexity, while maintaining high accuracy. Our study shows that DL can help increase the accuracy and true positive rate (TPR) of workload-aware models for a pipelined floating-point core compared to existing models. In addition, we demonstrate that removing up to 40% of the total neurons has minimal impact on the accuracy and overall predictive performance (up to 2.2%) of our DL-based timing error models, while significantly reducing the computational complexity. In fact, the complexity of the sparse model is approximately 2× smaller than the dense one.

U2 - 10.1109/ICCD58817.2023.00012

DO - 10.1109/ICCD58817.2023.00012

M3 - Conference contribution

AN - SCOPUS:85182326427

SN - 9798350342925

T3 - International Conference on Computer Design (ICCD) Proceedings

SP - 9

EP - 12

BT - Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 41st IEEE International Conference on Computer Design 2023

Y2 - 6 November 2023 through 8 November 2023

ER -

Tompazi S, Karakonstantis G. A compressed and accurate sparse deep learning-based workload-aware timing error model. In Proceedings of the 41st IEEE International Conference on Computer Design, ICCD 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 9-12. (International Conference on Computer Design (ICCD) Proceedings). doi: 10.1109/ICCD58817.2023.00012

A compressed and accurate sparse deep learning-based workload-aware timing error model

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Fingerprint

Student theses

Microarchitecture and workload-aware error prediction based on artificial intelligence

Cite this