A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

The PUF is a physical security primitive that permits to extract intrinsic digital identifiers from electronic devices. As low-cost nature PUF is a promising candidate to meet security in lightweight devices for IoT application. The Arbiter PUF or APUF has been widely studied in the technical literature. However it often suffers from disadvantages such as poor uniqueness and reliability, particularly when implemented on FPGAs due to features such as physical layout restrictions. To address these problems, a new design known as the FF-APUF has been proposed; it offers a compact architecture, combined with good uniqueness and reliability, as well as suitable for FPGA implementation. Many PUF designs have been shown to be vulnerable to ML based modeling attacks. In this paper, it is initially shown that the FF-APUF design requires more efforts than a conventional APUF design for the adversary to attack. A comprehensive analysis of the experimental results for the FF-APUF design is also presented. An improved APUF design with a balanced arbiter and a FF-APUF design are proposed and implemented on the Xilinx Artix-7 FPGA at 28 nm technology. The experimental min-entropy of the FF-APUF design across different devices is more than twice of a conventional APUF design.