A floating point CORDIC based SVD processor

Z. Liu, K. Dickson, J. V. McCanny

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

An SVD processor system is presented in which each processing element is implemented using a simple CORDIC unit. The internal recursive loop within the CORDIC module is exploited, with pipelining being used to multiplex the two independent micro-rotations onto a single CORDIC processor. This leads to a high performance and efficient hardware architecture. In addition, a novel method for scale factor correction is presented which only need be applied once at the end of the computation. This also reduces the computation time. The net result is an SVD architecture based on a conventional CORDIC approach, which combines high performance with high silicon area efficiency.

Original languageEnglish
Title of host publicationProceedings. IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2003
EditorsE Deprettere, S Bhattacharyya, J Cavallaro, A Darte, L Thiele
Place of PublicationLOS ALAMITOS
PublisherIEEE Computer Society
Pages194-203
Number of pages10
ISBN (Print)0-7695-1992-X
DOIs
Publication statusPublished - 2003
Event14th IEEE International Conference on Application-Specific Systems, Architectures and Processors - THE HAGUE, Netherlands
Duration: 24 Jun 200326 Jun 2003

Conference

Conference14th IEEE International Conference on Application-Specific Systems, Architectures and Processors
CountryNetherlands
CityTHE HAGUE
Period24/06/200326/06/2003

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  • Cite this

    Liu, Z., Dickson, K., & McCanny, J. V. (2003). A floating point CORDIC based SVD processor. In E. Deprettere, S. Bhattacharyya, J. Cavallaro, A. Darte, & L. Thiele (Eds.), Proceedings. IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2003 (pp. 194-203). IEEE Computer Society. https://doi.org/10.1109/ASAP.2003.1212843