A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

Xin Yang; Sakir Sezer; Shane O'Neill

doi:10.1109/SOCC.2014.6948969

A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

Xin Yang, Sakir Sezer, Shane O'Neill

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

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Abstract

This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

Original language	English
Title of host publication	2014 27th IEEE International System-on-Chip Conference (SOCC)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	437-442
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2014.6948969
Publication status	Published - 02 Sept 2014
Event	IEEE System-on-Chip Conference (SOCC) - Nevada, Las Vegas, United States Duration: 02 Sept 2014 → 05 Sept 2014

Conference

Conference	IEEE System-on-Chip Conference (SOCC)
Country/Territory	United States
City	Las Vegas
Period	02/09/2014 → 05/09/2014

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10.1109/SOCC.2014.6948969

A hardware acceleration scheme for memory-efficient flow processing
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Accepted author manuscript, 404 KB

R1118ECI: Centre for Secure Information Technologies (CSIT)
McCanny, J. V. (PI), Cowan, C. (CoI), Crookes, D. (CoI), Fusco, V. (CoI), Linton, D. (CoI), Liu, W. (CoI), Miller, P. (CoI), O'Neill, M. (CoI), Scanlon, W. (CoI) & Sezer, S. (CoI)
01/08/2009 → 30/06/2014
Project: Research

Cite this

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title = "A Hardware Acceleration Scheme for Memory-Efficient Flow Processing",

abstract = "This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.",

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AB - This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

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T2 - IEEE System-on-Chip Conference (SOCC)

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ER -

A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

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R1118ECI: Centre for Secure Information Technologies (CSIT)

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