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In this paper, a hardware solution for packet classification based on multi-fields is presented. The proposed scheme focuses on a new architecture based on the decomposition method. A hash circuit is used in order to reduce the memory space required for the Recursive Flow Classification (RFC) algorithm. The implementation results show that the proposed architecture achieves significant performance advantage that is comparable to that of some well-known algorithms. The solution is based on Altera Stratix III FPGA technology.
|Number of pages||5|
|Publication status||Accepted - Aug 2012|
|Event||UKEF12 - Newcastle, United Kingdom|
Duration: 30 Aug 2012 → 31 Aug 2012
|Period||30/08/2012 → 31/08/2012|