A hardware solution on multi-field packet classification

Keissy Guerra Perez, Xin Yang, Sakir Sezer

Research output: Contribution to conferencePaperpeer-review


In this paper, a hardware solution for packet classification based on multi-fields is presented. The proposed scheme focuses on a new architecture based on the decomposition method. A hash circuit is used in order to reduce the memory space required for the Recursive Flow Classification (RFC) algorithm. The implementation results show that the proposed architecture achieves significant performance advantage that is comparable to that of some well-known algorithms. The solution is based on Altera Stratix III FPGA technology.
Original languageEnglish
Number of pages5
Publication statusAccepted - Aug 2012
EventUKEF12 - Newcastle, United Kingdom
Duration: 30 Aug 201231 Aug 2012


Country/TerritoryUnited Kingdom


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