A high performance IIR digital filter chip

R.F. Woods, J.V. McCanny, S.C. Knowles, O.C. McNally

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Place of PublicationNEW YORK
PublisherAshgate Publishing
Pages1410-1413
Number of pages4
Volume2
Publication statusPublished - 1990
Event1990 INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS ( ISCAS 90 ) - NEW ORLEANS, United States
Duration: 01 May 199003 May 1990

Conference

Conference1990 INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS ( ISCAS 90 )
CountryUnited States
CityNEW ORLEANS
Period01/05/199003/05/1990

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Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

Cite this

Woods, R. F., McCanny, J. V., Knowles, S. C., & McNally, O. C. (1990). A high performance IIR digital filter chip. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2, pp. 1410-1413). NEW YORK: Ashgate Publishing.