Abstract
The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.
Original language | English |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Place of Publication | NEW YORK |
Publisher | Ashgate Publishing Ltd |
Pages | 1410-1413 |
Number of pages | 4 |
Volume | 2 |
Publication status | Published - 1990 |
Event | 1990 INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS ( ISCAS 90 ) - NEW ORLEANS, United States Duration: 01 May 1990 → 03 May 1990 |
Conference
Conference | 1990 INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS ( ISCAS 90 ) |
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Country/Territory | United States |
City | NEW ORLEANS |
Period | 01/05/1990 → 03/05/1990 |