A high performance vector quantisation chip

M. Yan; Y. Hu; J. V. McCanny

doi:10.1109/VLSISP.1993.404491

A high performance vector quantisation chip

M. Yan, Y. Hu, J. V. McCanny

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A demonstrator chip is described for real time speech vector quantisation applications. The chip has been fabricated in a 1.2 micron CMOS technology and contains 38,000 transistors. It occupies a die area of only (4.8 × 4.6) mm/sup 2 and can perform over 80 million multiply/accumulate operations per second. The chip fully demonstrates the benefits which result from using a regular dedicated VLSI architecture.

Original language	English
Title of host publication	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	159-167
Number of pages	9
ISBN (Electronic)	0780309960, 9780780309968
DOIs	https://doi.org/10.1109/VLSISP.1993.404491
Publication status	Published - 20 Oct 1993
Event	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands Duration: 20 Oct 1993 → 22 Oct 1993

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
Country/Territory	Netherlands
City	Veldhoven
Period	20/10/1993 → 22/10/1993

ASJC Scopus subject areas

Hardware and Architecture
Signal Processing
Software

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10.1109/VLSISP.1993.404491

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title = "A high performance vector quantisation chip",

abstract = "A demonstrator chip is described for real time speech vector quantisation applications. The chip has been fabricated in a 1.2 micron CMOS technology and contains 38,000 transistors. It occupies a die area of only (4.8 × 4.6) mm/sup 2 and can perform over 80 million multiply/accumulate operations per second. The chip fully demonstrates the benefits which result from using a regular dedicated VLSI architecture.",

author = "M. Yan and Y. Hu and McCanny, {J. V.}",

year = "1993",

month = oct,

day = "20",

doi = "10.1109/VLSISP.1993.404491",

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booktitle = "Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993",

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note = "6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 ; Conference date: 20-10-1993 Through 22-10-1993",

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AB - A demonstrator chip is described for real time speech vector quantisation applications. The chip has been fabricated in a 1.2 micron CMOS technology and contains 38,000 transistors. It occupies a die area of only (4.8 × 4.6) mm/sup 2 and can perform over 80 million multiply/accumulate operations per second. The chip fully demonstrates the benefits which result from using a regular dedicated VLSI architecture.

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U2 - 10.1109/VLSISP.1993.404491

DO - 10.1109/VLSISP.1993.404491

M3 - Conference contribution

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BT - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993

Y2 - 20 October 1993 through 22 October 1993

ER -

A high performance vector quantisation chip

Abstract

Conference

ASJC Scopus subject areas

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