A high performance vector quantisation chip

M. Yan, Y. Hu, J. V. McCanny

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A demonstrator chip is described for real time speech vector quantisation applications. The chip has been fabricated in a 1.2 micron CMOS technology and contains 38,000 transistors. It occupies a die area of only (4.8 × 4.6) mm/sup 2 and can perform over 80 million multiply/accumulate operations per second. The chip fully demonstrates the benefits which result from using a regular dedicated VLSI architecture.

Original languageEnglish
Title of host publicationProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages9
ISBN (Electronic)0780309960, 9780780309968
Publication statusPublished - 20 Oct 1993
Event6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands
Duration: 20 Oct 199322 Oct 1993


Conference6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing
  • Software


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