Abstract
As a lightweight hardware security primitive, physical unclonable functions (PUFs) can provide reliable identity authentication for the Internet of Things (IoT) devices with limited resources. Arbiter PUF (APUF) is one of the most well-known PUF circuits. However, its hardware implementation has poor reliability on field programmable gate arrays (FPGAs). This paper proposed a highly reliable APUF that uses a delay difference quantization strategy (DDQ-APUF). By adding multiple configurable delay units to the two symmetrical paths of the conventional APUF, the delay difference between the two symmetrical paths of APUF can be obtained by collecting the output of APUF under different delay configurations. Compared to conventional APUFs, DDQ-APUF does not use the arbitration result of signal transmission in two symmetric paths as its response, but rather uses the quantified delay difference between the two paths as its response. A tolerance threshold is adopted in the authentication to accommodate the variations in delay differences due to environmental changes. Moreover, the modeling attack resistance of DDQ-APUF is evaluated, and a strategy for improving this resistance by incorporating pseudo-XOR technique is proposed. The circuit was implemented on Xilinx Artix-7 FPGAs and the experimental results show that the reliability achieves 99.95 % with non-CRP-discard.
Original language | English |
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Number of pages | 13 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Early online date | 08 Oct 2024 |
DOIs | |
Publication status | Early online date - 08 Oct 2024 |
Publications and Copyright Policy
This work is licensed under Queen’s Research Publications and Copyright Policy.Keywords
- lightweight hardware security primitive
- PUFs
- Internet of Things
- IoTs
- FPGAs
- security
- authentication