A High Throughput FPGA Implementation of a Bit-Level Matrix Product

Abbes Amira, Ahmed Bouridane, Peter Milligan, Paul Sage

Research output: Contribution to conferencePaper

21 Citations (Scopus)
Original languageEnglish
Pages356-364
Number of pages9
Publication statusPublished - Oct 2000
EventIEEE Workshop on Signal Processing Systems Design and Implementation - Lafayette, United States
Duration: 01 Oct 200001 Oct 2000

Conference

ConferenceIEEE Workshop on Signal Processing Systems Design and Implementation
CountryUnited States
CityLafayette
Period01/10/200001/10/2000

Cite this

Amira, A., Bouridane, A., Milligan, P., & Sage, P. (2000). A High Throughput FPGA Implementation of a Bit-Level Matrix Product. 356-364. Paper presented at IEEE Workshop on Signal Processing Systems Design and Implementation, Lafayette, United States.
Amira, Abbes ; Bouridane, Ahmed ; Milligan, Peter ; Sage, Paul. / A High Throughput FPGA Implementation of a Bit-Level Matrix Product. Paper presented at IEEE Workshop on Signal Processing Systems Design and Implementation, Lafayette, United States.9 p.
@conference{0c0e507342ac4e15adb9096c45d522d2,
title = "A High Throughput FPGA Implementation of a Bit-Level Matrix Product",
author = "Abbes Amira and Ahmed Bouridane and Peter Milligan and Paul Sage",
year = "2000",
month = "10",
language = "English",
pages = "356--364",
note = "IEEE Workshop on Signal Processing Systems Design and Implementation ; Conference date: 01-10-2000 Through 01-10-2000",

}

Amira, A, Bouridane, A, Milligan, P & Sage, P 2000, 'A High Throughput FPGA Implementation of a Bit-Level Matrix Product', Paper presented at IEEE Workshop on Signal Processing Systems Design and Implementation, Lafayette, United States, 01/10/2000 - 01/10/2000 pp. 356-364.

A High Throughput FPGA Implementation of a Bit-Level Matrix Product. / Amira, Abbes; Bouridane, Ahmed; Milligan, Peter; Sage, Paul.

2000. 356-364 Paper presented at IEEE Workshop on Signal Processing Systems Design and Implementation, Lafayette, United States.

Research output: Contribution to conferencePaper

TY - CONF

T1 - A High Throughput FPGA Implementation of a Bit-Level Matrix Product

AU - Amira, Abbes

AU - Bouridane, Ahmed

AU - Milligan, Peter

AU - Sage, Paul

PY - 2000/10

Y1 - 2000/10

M3 - Paper

SP - 356

EP - 364

ER -

Amira A, Bouridane A, Milligan P, Sage P. A High Throughput FPGA Implementation of a Bit-Level Matrix Product. 2000. Paper presented at IEEE Workshop on Signal Processing Systems Design and Implementation, Lafayette, United States.