A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors

Chengwei Zheng, John McAllister, Yun Wu

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

Massively parallel networks of highly efficient, high performance Single Instruction Multiple Data (SIMD) processors have been shown to enable FPGA-based implementation of real-time signal processing applications with performance and
cost comparable to dedicated hardware architectures. This is achieved by exploiting simple datapath units with deep processing pipelines. However, these architectures are highly susceptible to pipeline bubbles resulting from data and control hazards; the only way to mitigate against these is manual interleaving of
application tasks on each datapath, since no suitable automated interleaving approach exists. In this paper we describe a new automated integrated mapping/scheduling approach to map algorithm tasks to processors and a new low-complexity list scheduling technique to generate the interleaved schedules. When applied to a spatial Fixed-Complexity Sphere Decoding (FSD) detector
for next-generation Multiple-Input Multiple-Output (MIMO) systems, the resulting schedules achieve real-time performance for IEEE 802.11n systems on a network of 16-way SIMD processors on FPGA, enable better performance/complexity balance than current approaches and produce results comparable to handcrafted implementations.
Original languageEnglish
Pages278 -285
Number of pages8
DOIs
Publication statusPublished - Jul 2011
Event2011 IEEE International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XI) - Samos, Greece
Duration: 18 Jul 201121 Jul 2011

Conference

Conference2011 IEEE International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XI)
CountryGreece
CitySamos
Period18/07/201121/07/2011

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    Zheng, C., McAllister, J., & Wu, Y. (2011). A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors. 278 -285. Paper presented at 2011 IEEE International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XI), Samos, Greece. https://doi.org/10.1109/SAMOS.2011.6045472