A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs

Chongyan Gu, Chip Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Maire O'Neill

Research output: Contribution to journalArticlepeer-review

Abstract

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator (TRNG), in field programmable gate array (FPGA) are crucial replacement of the conventional decryption key stored in batterybacked random-access memory (RAM) or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA, is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (PicoPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single C. Gu*, N. Hanley, J. Miskelly and M. O’Neill Centre for Secure Information Technologies (CSIT) Queen’s University Belfast, Belfast, U.K. E-mail: {cgu01, n.hanley, jmiskelly}@qub.ac.uk E-mail: m.oneill@ecit.qub.ac.uk C. H. Chang School of Electrical and Electronic Engineering Nanyang Technological University, Singapore E-mail: echchang@ntu.edu.sg W. Liu* College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics Nanjing, China E-mail: liuweiqiang@nuaa.edu.cn * corresponding authors slice disorder-based security entities have been investigated and compared on 28nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bitaliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the minentropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF (RO PUF) and some existing memory based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design is made publicly available to enable the research community to use them for benchmarking and/or validation.  
Original languageEnglish
JournalJournal of Cryptographic Engineering
Publication statusAccepted - 07 Oct 2020

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