Abstract
| Language | English |
|---|---|
| Title of host publication | 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings |
| Publisher | IEEE Circuits and Systems Society |
| Pages | 97-104 |
| Number of pages | 8 |
| ISBN (Electronic) | 978-1-5090-0602-1 |
| ISBN (Print) | 978-1-5090-0603-8 |
| DOIs | |
| Publication status | Published - 22 Feb 2018 |
| Event | 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - Jeju, Korea, Republic of Duration: 22 Jan 2018 → 25 Jan 2018 http://ieeexplore.ieee.org/abstract/document/8297289/ |
Publication series
| Name | 23rd Asia and South Pacific Design Automation Conference |
|---|---|
| Publisher | IEEE |
| ISSN (Electronic) | 2153-697X |
Conference
| Conference | 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) |
|---|---|
| Country | Korea, Republic of |
| City | Jeju |
| Period | 22/01/2018 → 25/01/2018 |
| Internet address |
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A Machine Learning Attack Resistant Multi-PUF Design on FPGA. / Ma, Qingqing; Gu, Chongyan; Hanley, Neil; Wang, Chenghua; Liu, Weiqiang; O'Neill, Maire.
23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. IEEE Circuits and Systems Society, 2018. p. 97-104 (23rd Asia and South Pacific Design Automation Conference ).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A Machine Learning Attack Resistant Multi-PUF Design on FPGA
AU - Ma, Qingqing
AU - Gu, Chongyan
AU - Hanley, Neil
AU - Wang, Chenghua
AU - Liu, Weiqiang
AU - O'Neill, Maire
PY - 2018/2/22
Y1 - 2018/2/22
N2 - Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.
AB - Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.
U2 - 10.1109/ASPDAC.2018.8297289
DO - 10.1109/ASPDAC.2018.8297289
M3 - Conference contribution
SN - 978-1-5090-0603-8
T3 - 23rd Asia and South Pacific Design Automation Conference
SP - 97
EP - 104
BT - 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings
PB - IEEE Circuits and Systems Society
ER -