A Machine Learning Attack Resistant Multi-PUF Design on FPGA

Qingqing Ma; Chongyan Gu; Neil Hanley; Chenghua Wang; Weiqiang Liu; Maire O'Neill

doi:10.1109/ASPDAC.2018.8297289

A Machine Learning Attack Resistant Multi-PUF Design on FPGA

Qingqing Ma, Chongyan Gu, Neil Hanley, Chenghua Wang, Weiqiang Liu, Maire O'Neill

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

61 Citations (Scopus)

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Abstract

Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.

Original language	English
Title of host publication	23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	97-104
Number of pages	8
ISBN (Electronic)	978-1-5090-0602-1
ISBN (Print)	978-1-5090-0603-8
DOIs	https://doi.org/10.1109/ASPDAC.2018.8297289
Publication status	Published - 22 Feb 2018
Event	2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - Jeju, Korea, Republic of Duration: 22 Jan 2018 → 25 Jan 2018 http://ieeexplore.ieee.org/abstract/document/8297289/

Publication series

Name	23rd Asia and South Pacific Design Automation Conference
Publisher	IEEE
ISSN (Electronic)	2153-697X

Conference

Conference	2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Country/Territory	Korea, Republic of
City	Jeju
Period	22/01/2018 → 25/01/2018
Internet address	http://ieeexplore.ieee.org/abstract/document/8297289/

Access to Document

10.1109/ASPDAC.2018.8297289Licence: Unspecified

A Machine Learning Attack Resistant Multi-PUF Design on FPGA
© 2018 IEEE. This work is made available online in accordance with the publisher’s policies. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 816 KBLicence: Unspecified

Cite this

Ma, Q., Gu, C., Hanley, N., Wang, C., Liu, W., & O'Neill, M. (2018). A Machine Learning Attack Resistant Multi-PUF Design on FPGA. In 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings (pp. 97-104). (23rd Asia and South Pacific Design Automation Conference ). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297289

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title = "A Machine Learning Attack Resistant Multi-PUF Design on FPGA",

abstract = "Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.",

author = "Qingqing Ma and Chongyan Gu and Neil Hanley and Chenghua Wang and Weiqiang Liu and Maire O'Neill",

year = "2018",

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doi = "10.1109/ASPDAC.2018.8297289",

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Ma, Q, Gu, C , Hanley, N, Wang, C, Liu, W & O'Neill, M 2018, A Machine Learning Attack Resistant Multi-PUF Design on FPGA. in 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. 23rd Asia and South Pacific Design Automation Conference , Institute of Electrical and Electronics Engineers Inc., pp. 97-104, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju, Korea, Republic of, 22/01/2018. https://doi.org/10.1109/ASPDAC.2018.8297289

A Machine Learning Attack Resistant Multi-PUF Design on FPGA. / Ma, Qingqing; Gu, Chongyan ; Hanley, Neil et al.
23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 97-104 (23rd Asia and South Pacific Design Automation Conference ).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A Machine Learning Attack Resistant Multi-PUF Design on FPGA

AU - Ma, Qingqing

AU - Gu, Chongyan

AU - Hanley, Neil

AU - Wang, Chenghua

AU - Liu, Weiqiang

AU - O'Neill, Maire

PY - 2018/2/22

Y1 - 2018/2/22

N2 - Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.

AB - Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.

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M3 - Conference contribution

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T3 - 23rd Asia and South Pacific Design Automation Conference

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BT - 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 22 January 2018 through 25 January 2018

ER -

A Machine Learning Attack Resistant Multi-PUF Design on FPGA

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