A Machine Learning Attack Resistant Multi-PUF Design on FPGA

Qingqing Ma, Chongyan Gu, Neil Hanley, Chenghua Wang, Weiqiang Liu, Maire O'Neill

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.
LanguageEnglish
Title of host publication23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings
PublisherIEEE Circuits and Systems Society
Pages97-104
Number of pages8
ISBN (Electronic)978-1-5090-0602-1
ISBN (Print)978-1-5090-0603-8
DOIs
Publication statusPublished - 22 Feb 2018
Event2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - Jeju, Korea, Republic of
Duration: 22 Jan 201825 Jan 2018
http://ieeexplore.ieee.org/abstract/document/8297289/

Publication series

Name23rd Asia and South Pacific Design Automation Conference
PublisherIEEE
ISSN (Electronic)2153-697X

Conference

Conference2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
CountryKorea, Republic of
CityJeju
Period22/01/201825/01/2018
Internet address

Fingerprint

Learning systems
Field programmable gate arrays (FPGA)
Hardware security
Mathematical models

Cite this

Ma, Q., Gu, C., Hanley, N., Wang, C., Liu, W., & O'Neill, M. (2018). A Machine Learning Attack Resistant Multi-PUF Design on FPGA. In 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings (pp. 97-104). (23rd Asia and South Pacific Design Automation Conference ). IEEE Circuits and Systems Society. https://doi.org/10.1109/ASPDAC.2018.8297289
Ma, Qingqing ; Gu, Chongyan ; Hanley, Neil ; Wang, Chenghua ; Liu, Weiqiang ; O'Neill, Maire. / A Machine Learning Attack Resistant Multi-PUF Design on FPGA. 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. IEEE Circuits and Systems Society, 2018. pp. 97-104 (23rd Asia and South Pacific Design Automation Conference ).
@inproceedings{ffd5ade8892849639be1cff631746b6c,
title = "A Machine Learning Attack Resistant Multi-PUF Design on FPGA",
abstract = "Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 {\%} and uniformity of 37.03 {\%}, which significantly improves over previous work into multi-PUF designs.",
author = "Qingqing Ma and Chongyan Gu and Neil Hanley and Chenghua Wang and Weiqiang Liu and Maire O'Neill",
year = "2018",
month = "2",
day = "22",
doi = "10.1109/ASPDAC.2018.8297289",
language = "English",
isbn = "978-1-5090-0603-8",
series = "23rd Asia and South Pacific Design Automation Conference",
publisher = "IEEE Circuits and Systems Society",
pages = "97--104",
booktitle = "23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings",
address = "United States",

}

Ma, Q, Gu, C, Hanley, N, Wang, C, Liu, W & O'Neill, M 2018, A Machine Learning Attack Resistant Multi-PUF Design on FPGA. in 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. 23rd Asia and South Pacific Design Automation Conference , IEEE Circuits and Systems Society, pp. 97-104, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju, Korea, Republic of, 22/01/2018. https://doi.org/10.1109/ASPDAC.2018.8297289

A Machine Learning Attack Resistant Multi-PUF Design on FPGA. / Ma, Qingqing; Gu, Chongyan; Hanley, Neil; Wang, Chenghua; Liu, Weiqiang; O'Neill, Maire.

23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. IEEE Circuits and Systems Society, 2018. p. 97-104 (23rd Asia and South Pacific Design Automation Conference ).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A Machine Learning Attack Resistant Multi-PUF Design on FPGA

AU - Ma, Qingqing

AU - Gu, Chongyan

AU - Hanley, Neil

AU - Wang, Chenghua

AU - Liu, Weiqiang

AU - O'Neill, Maire

PY - 2018/2/22

Y1 - 2018/2/22

N2 - Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.

AB - Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult to implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises a Weak PUF to obfuscate the challenges to a Strong PUF and is harder to model than the conventional arbiter PUF using machine learning attacks. The proposed PUF design shows a greater resistance to attacks, which have been successfully applied to other Arbiter PUFs. A mathematical model is presented to analyse the complexity and obfuscation properties of the proposed PUF design. Moreover, we show that it is feasible to implement the proposed MPUF design on a Xilinx Artix-7 FPGA, and that it achieves a good uniqueness result of 40.60 % and uniformity of 37.03 %, which significantly improves over previous work into multi-PUF designs.

U2 - 10.1109/ASPDAC.2018.8297289

DO - 10.1109/ASPDAC.2018.8297289

M3 - Conference contribution

SN - 978-1-5090-0603-8

T3 - 23rd Asia and South Pacific Design Automation Conference

SP - 97

EP - 104

BT - 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings

PB - IEEE Circuits and Systems Society

ER -

Ma Q, Gu C, Hanley N, Wang C, Liu W, O'Neill M. A Machine Learning Attack Resistant Multi-PUF Design on FPGA. In 23rd Asia and South Pacific Design Automation Conference (ASP-DAC): Proceedings. IEEE Circuits and Systems Society. 2018. p. 97-104. (23rd Asia and South Pacific Design Automation Conference ). https://doi.org/10.1109/ASPDAC.2018.8297289