Hardware Trojans (HTs) are acknowledged as a significant emerging security concern in the IC industry resulting from the globalization of the semiconductor supply chain. Recently, taking advantage of the exponential growth in computing power, machine learning (ML) approaches such as neural networks (NNs) are being considered for HT detection. However, the circuit structure and components of an IC design are different from the data types in the ML models. To efficiently extract HT features from complex IC designs and utilize common ML-based detection approaches is challenging. In this paper, a novel HT feature extraction strategy based on gate-level circuit netlists is proposed to tackle the challenges. The HT features are extracted from the circuit topology rather than statistical analysis in previous research. A commonly utilized support vector machine (SVM)-based HT detection model is employed for data training and testing using the extracted features on HT benchmarks from both open-sourced library and HT generation platform to prove the feasibility and efficiency of the proposed HT feature extraction strategy. The detection results show high recall in nearly all tested benchmarks, achieving at most 97.7% recall on sequential Trojans and 84.8% on combinational ones.
|Title of host publication||The IEEE International Symposium on Circuits and Systems (ISCAS)|
|Publication status||Accepted - 05 Jan 2020|
|Event||The IEEE International Symposium on Circuits and Systems 2020 - Hotel Barceló Sevilla Renacimiento, Sevilla, Spain|
Duration: 17 May 2020 → 20 May 2020
Conference number: 2020
|Conference||The IEEE International Symposium on Circuits and Systems 2020|
|Period||17/05/2020 → 20/05/2020|
- Hardware Trojans
- Feature extraction
- Circuit topology
- Machine learning
Yu, S., Gu, C., Liu, W., & O'Neill, M. (Accepted/In press). A Novel Feature Extraction Strategy for Hardware Trojan Detection. In The IEEE International Symposium on Circuits and Systems (ISCAS) IEEE .