A novel FPGA mutually coupled configurable ring oscillator PUF

James Moore; Jack Miskelly; Máire O'Neill; Chongyan Gu

doi:10.1109/AsianHOST63913.2024.10838475

A novel FPGA mutually coupled configurable ring oscillator PUF

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This Paper presents a novel method to increase the complexity of configurable ring oscillator PUFs on Xilinx 7 series FPGAs by taking advantage of mutual coupling between two ring oscillators. The primary motivation behind this is to improve machine learning resistance of PUFs while maintaining a lightweight architecture. By using this method it was possible to achieve a non linear relationship between the challenge and response giving this lightweight PUF excellent machine learning resistance with a max prediction rate of 55% with 2.9 Million CRPs. This out preforms other designs of this size. The proposed design also achieved an uniqueness of 0.456 over 100 devices and a total error rate of 3.027% over 20 devices with 85% of the CPRs being fully reliable.

Original language	English
Title of host publication	Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2024): Proceedings
Place of Publication	Kobe, Japan
Publisher	IEEE Xplore
Number of pages	6
ISBN (Electronic)	9798350368062
ISBN (Print)	9798350368079
DOIs	https://doi.org/10.1109/AsianHOST63913.2024.10838475
Publication status	Published - 16 Jan 2025
Event	IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) - Kobe, Japan Duration: 16 Dec 2024 → 18 Dec 2024

Conference

Conference	IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST)
Country/Territory	Japan
City	Kobe
Period	16/12/2024 → 18/12/2024

Keywords

ring oscillators
resistance
error analysis

Access to Document

10.1109/AsianHOST63913.2024.10838475Licence: Unspecified

Cite this

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title = "A novel FPGA mutually coupled configurable ring oscillator PUF",

abstract = "This Paper presents a novel method to increase the complexity of configurable ring oscillator PUFs on Xilinx 7 series FPGAs by taking advantage of mutual coupling between two ring oscillators. The primary motivation behind this is to improve machine learning resistance of PUFs while maintaining a lightweight architecture. By using this method it was possible to achieve a non linear relationship between the challenge and response giving this lightweight PUF excellent machine learning resistance with a max prediction rate of 55\% with 2.9 Million CRPs. This out preforms other designs of this size. The proposed design also achieved an uniqueness of 0.456 over 100 devices and a total error rate of 3.027\% over 20 devices with 85\% of the CPRs being fully reliable. ",

keywords = "ring oscillators, resistance, error analysis",

author = "James Moore and Jack Miskelly and M{\'a}ire O'Neill and Chongyan Gu",

year = "2025",

month = jan,

day = "16",

doi = "10.1109/AsianHOST63913.2024.10838475",

language = "English",

isbn = "9798350368079",

booktitle = "Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2024): Proceedings",

publisher = "IEEE Xplore",

note = "IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) ; Conference date: 16-12-2024 Through 18-12-2024",

}

Moore, J , Miskelly, J , O'Neill, M & Gu, C 2025, A novel FPGA mutually coupled configurable ring oscillator PUF. in Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2024): Proceedings. IEEE Xplore, Kobe, Japan, IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Kobe, Japan, 16/12/2024. https://doi.org/10.1109/AsianHOST63913.2024.10838475

TY - GEN

T1 - A novel FPGA mutually coupled configurable ring oscillator PUF

AU - Moore, James

AU - Miskelly, Jack

AU - O'Neill, Máire

AU - Gu, Chongyan

PY - 2025/1/16

Y1 - 2025/1/16

N2 - This Paper presents a novel method to increase the complexity of configurable ring oscillator PUFs on Xilinx 7 series FPGAs by taking advantage of mutual coupling between two ring oscillators. The primary motivation behind this is to improve machine learning resistance of PUFs while maintaining a lightweight architecture. By using this method it was possible to achieve a non linear relationship between the challenge and response giving this lightweight PUF excellent machine learning resistance with a max prediction rate of 55% with 2.9 Million CRPs. This out preforms other designs of this size. The proposed design also achieved an uniqueness of 0.456 over 100 devices and a total error rate of 3.027% over 20 devices with 85% of the CPRs being fully reliable.

AB - This Paper presents a novel method to increase the complexity of configurable ring oscillator PUFs on Xilinx 7 series FPGAs by taking advantage of mutual coupling between two ring oscillators. The primary motivation behind this is to improve machine learning resistance of PUFs while maintaining a lightweight architecture. By using this method it was possible to achieve a non linear relationship between the challenge and response giving this lightweight PUF excellent machine learning resistance with a max prediction rate of 55% with 2.9 Million CRPs. This out preforms other designs of this size. The proposed design also achieved an uniqueness of 0.456 over 100 devices and a total error rate of 3.027% over 20 devices with 85% of the CPRs being fully reliable.

KW - ring oscillators

KW - resistance

KW - error analysis

U2 - 10.1109/AsianHOST63913.2024.10838475

DO - 10.1109/AsianHOST63913.2024.10838475

M3 - Conference contribution

SN - 9798350368079

BT - Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2024): Proceedings

PB - IEEE Xplore

CY - Kobe, Japan

T2 - IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST)

Y2 - 16 December 2024 through 18 December 2024

ER -

A novel FPGA mutually coupled configurable ring oscillator PUF

Abstract

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Keywords

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