A novel methodology for processor based PUF in approximate computing

Approximate computing has great potential in the design of high-performance and energy-efficient systems. The inherent stochastic error behavior of approximate computing introduces both new security threats and opportunities to enhance security. This work proposes a novel methodology that exploits stochastic timing errors of a pipelined datapath to design a processor based physically unclonable function (PUF) for approximate computing. This methodology uses divergent delay path selection based on intermediary error behaviour to improve the PUF uniqueness vs. an unmodified datapath, even when only moderate voltage scaling is applied. To verify the effectiveness of this method, a pipelined fast fourier transform (FFT) butterfly architecture is implemented at 45nm technology node, and a voltage over scaling technique is applied to extract PUF bits. The proposed methodology achieves a maximum uniqueness of 48.5% whereas conventional design uniqueness is limited to 43%. Overall, the proposed design shows a maximum of ~7% higher uniqueness and ~10% higher reliability (for iso uniqueness) compared to the conventional pipelined design.