A parallel pattern for iterative stencil + reduce

M. Aldinucci, M. Danelutto, M. Drocco, P. Kilpatrick, C. Misale, G. Peretti Pezzi, M. Torquati

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)
439 Downloads (Pure)

Abstract

We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.
Original languageEnglish
Pages (from-to)5690-5705
Number of pages16
JournalThe Journal of Supercomputing
Volume74
Issue number11
Early online date08 Sep 2016
DOIs
Publication statusPublished - 01 Nov 2018

Keywords

  • cs.DC

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