TY - JOUR
T1 - A Physical Unclonable Function using a Configurable Tristate Hybrid Scheme with Non-Volatile Memory
AU - Li, Jiang
AU - Cui, Yijun
AU - Gu, Chongyan
AU - Wang, Chenghua
AU - Liu, Weiqiang
AU - Lombardi, Fabrizio
PY - 2021/2/9
Y1 - 2021/2/9
N2 - The physical unclonable function (PUF) is a promising low-cost hardware security primitive. Recent advances in nanotechnology have provided new opportunities for nanoscale PUF circuits. The resistive random access memory (RRAM) is extensively used in nanoscale circuits due to its low cost, non-volatility and easy integration with CMOS. This paper proposes a novel tristate hybrid PUF (TH-PUF) design based on a one-transistor-one-RRAM (1T1R) cell; this cell can be configured into two weak PUFs and a strong PUF using few control signals. To assess the proposed PUF design, a compact RRAM model at UMC 65 nm technology is employed. Simulation results show that the proposed TH-PUF achieves good uniqueness, reliability as well as a higher gate usability compared with an entire CMOS PUFs. The number of challenge response pairs (CRPs) of the proposed TH-PUF is larger than other RRAM-based PUFs. Moreover, the TH-PUF is more resistant to a modeling machine learning attack than traditional PUF designs
AB - The physical unclonable function (PUF) is a promising low-cost hardware security primitive. Recent advances in nanotechnology have provided new opportunities for nanoscale PUF circuits. The resistive random access memory (RRAM) is extensively used in nanoscale circuits due to its low cost, non-volatility and easy integration with CMOS. This paper proposes a novel tristate hybrid PUF (TH-PUF) design based on a one-transistor-one-RRAM (1T1R) cell; this cell can be configured into two weak PUFs and a strong PUF using few control signals. To assess the proposed PUF design, a compact RRAM model at UMC 65 nm technology is employed. Simulation results show that the proposed TH-PUF achieves good uniqueness, reliability as well as a higher gate usability compared with an entire CMOS PUFs. The number of challenge response pairs (CRPs) of the proposed TH-PUF is larger than other RRAM-based PUFs. Moreover, the TH-PUF is more resistant to a modeling machine learning attack than traditional PUF designs
U2 - 10.1109/OJNANO.2021.3058169
DO - 10.1109/OJNANO.2021.3058169
M3 - Article
VL - 2
SP - 31
EP - 40
JO - IEEE Open Journal of Nanotechnology
JF - IEEE Open Journal of Nanotechnology
ER -