A Scalable and Programmable Modular Traffic Manager Architecture

Shane O'Neill, Roger Woods, Alan Marshall, Qi Zhang

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)
3 Downloads (Pure)


A key issue in the design of next generation Internet routers and switches will be provision of traffic manager (TM) functionality in the datapaths of their high speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g. drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.
Original languageEnglish
Article number14
JournalACM Transactions on Reconfigurable Technology and Systems
Issue number2
Publication statusPublished - May 2011

ASJC Scopus subject areas

  • Computer Science(all)


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