A scalable packet sorting circuit for high-speed WFQ packet scheduling

Kieran McLaughlin; Sakir Sezer; Holger Blume; Xin Yang; Friederich Kupzog; Tobias Noll

doi:10.1109/TVLSI.2008.2000323

A scalable packet sorting circuit for high-speed WFQ packet scheduling

Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias Noll

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Original language	English
Article number	4553746
Pages (from-to)	781-791
Number of pages	11
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	16
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2008.2000323
Publication status	Published - Jul 2008

Keywords

Packet scheduling
traffic management
quality of servcie
QoS
lookup
sorting
fair queuing
WFQ
time-stamp

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture

Access to Document

10.1109/TVLSI.2008.2000323

Cite this

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abstract = "A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.",

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