A scalable packet sorting circuit for high-speed WFQ packet scheduling

Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias Noll

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)


A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
Original languageEnglish
Article number4553746
Pages (from-to)781-791
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
Publication statusPublished - Jul 2008


  • Packet scheduling
  • traffic management
  • quality of servcie
  • QoS
  • lookup
  • sorting
  • fair queuing
  • WFQ
  • time-stamp

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture


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