Abstract
A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
| Original language | English |
|---|---|
| Article number | 4553746 |
| Pages (from-to) | 781-791 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 16 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - Jul 2008 |
Keywords
- Packet scheduling
- traffic management
- quality of servcie
- QoS
- lookup
- sorting
- fair queuing
- WFQ
- time-stamp
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
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Cite this
McLaughlin, K., Sezer, S., Blume, H., Yang, X., Kupzog, F., & Noll, T. (2008). A scalable packet sorting circuit for high-speed WFQ packet scheduling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(7), 781-791. [4553746]. https://doi.org/10.1109/TVLSI.2008.2000323