A unique and robust single slice FPGA identification generator

Chongyan Gu; Julian Murphy; Maire O'Neill

doi:10.1109/ISCAS.2014.6865362

A unique and robust single slice FPGA identification generator

Chongyan Gu, Julian Murphy, Maire O'Neill

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

Original language	English
Title of host publication	Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1223-1226
Number of pages	4
ISBN (Print)	9781479934317
DOIs	https://doi.org/10.1109/ISCAS.2014.6865362
Publication status	Published - 01 Jun 2014
Event	IEEE International Symposium on Circuits and Systems - Melbourne, Australia Duration: 01 Jun 2014 → 07 Jun 2014

Conference

Conference	IEEE International Symposium on Circuits and Systems
Country	Australia
City	Melbourne
Period	01/06/2014 → 07/06/2014

Access to Document

10.1109/ISCAS.2014.6865362

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6865362&refinements%3D4276062589%26sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6865048%29

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Projects

1 Finished

R1118ECI: Centre for Secure Information Technologies (CSIT)

McCanny, J. V., Cowan, C., Crookes, D., Fusco, V., Linton, D., Liu, W., Miller, P., O'Neill, M., Scanlon, W. & Sezer, S.

01/08/2009 → 30/06/2014

Project: Research

Cite this

Gu, C., Murphy, J., & O'Neill, M. (2014). A unique and robust single slice FPGA identification generator. In Circuits and Systems (ISCAS), 2014 IEEE International Symposium on (pp. 1223-1226). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISCAS.2014.6865362

@inproceedings{4a1457e8d5e44ff0afb05fbf67d9f413,

title = "A unique and robust single slice FPGA identification generator",

abstract = "In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage",

author = "Chongyan Gu and Julian Murphy and Maire O'Neill",

year = "2014",

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doi = "10.1109/ISCAS.2014.6865362",

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isbn = "9781479934317",

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booktitle = "Circuits and Systems (ISCAS), 2014 IEEE International Symposium on",

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Gu, C, Murphy, J & O'Neill, M 2014, A unique and robust single slice FPGA identification generator. in Circuits and Systems (ISCAS), 2014 IEEE International Symposium on. Institute of Electrical and Electronics Engineers (IEEE), pp. 1223-1226, IEEE International Symposium on Circuits and Systems, Melbourne, Australia, 01/06/2014. https://doi.org/10.1109/ISCAS.2014.6865362

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N2 - In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

AB - In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

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