A unique and robust single slice FPGA identification generator

Chongyan Gu; Julian Murphy; Maire O'Neill

doi:10.1109/ISCAS.2014.6865362

A unique and robust single slice FPGA identification generator

Chongyan Gu, Julian Murphy, Maire O'Neill

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

32 Citations (Scopus)

Abstract

In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

Original language	English
Title of host publication	Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1223-1226
Number of pages	4
ISBN (Print)	9781479934317
DOIs	https://doi.org/10.1109/ISCAS.2014.6865362
Publication status	Published - 01 Jun 2014
Event	IEEE International Symposium on Circuits and Systems - Melbourne, Australia Duration: 01 Jun 2014 → 07 Jun 2014

Conference

Conference	IEEE International Symposium on Circuits and Systems
Country/Territory	Australia
City	Melbourne
Period	01/06/2014 → 07/06/2014

Access to Document

10.1109/ISCAS.2014.6865362

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6865362&refinements%3D4276062589%26sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6865048%29

R1118ECI: Centre for Secure Information Technologies (CSIT)
McCanny, J. V. (PI), Cowan, C. (CoI), Crookes, D. (CoI), Fusco, V. (CoI), Linton, D. (CoI), Liu, W. (CoI), Miller, P. (CoI), O'Neill, M. (CoI), Scanlon, W. (CoI) & Sezer, S. (CoI)
01/08/2009 → 30/06/2014
Project: Research

Cite this

@inproceedings{4a1457e8d5e44ff0afb05fbf67d9f413,

title = "A unique and robust single slice FPGA identification generator",

abstract = "In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage",

author = "Chongyan Gu and Julian Murphy and Maire O'Neill",

year = "2014",

month = jun,

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doi = "10.1109/ISCAS.2014.6865362",

language = "English",

isbn = "9781479934317",

pages = "1223--1226",

booktitle = "Circuits and Systems (ISCAS), 2014 IEEE International Symposium on",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems ; Conference date: 01-06-2014 Through 07-06-2014",

}

Gu, C, Murphy, J & O'Neill, M 2014, A unique and robust single slice FPGA identification generator. in Circuits and Systems (ISCAS), 2014 IEEE International Symposium on. Institute of Electrical and Electronics Engineers Inc., pp. 1223-1226, IEEE International Symposium on Circuits and Systems, Melbourne, Australia, 01/06/2014. https://doi.org/10.1109/ISCAS.2014.6865362

TY - GEN

T1 - A unique and robust single slice FPGA identification generator

AU - Gu, Chongyan

AU - Murphy, Julian

AU - O'Neill, Maire

PY - 2014/6/1

Y1 - 2014/6/1

N2 - In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

AB - In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage

U2 - 10.1109/ISCAS.2014.6865362

DO - 10.1109/ISCAS.2014.6865362

M3 - Conference contribution

SN - 9781479934317

SP - 1223

EP - 1226

BT - Circuits and Systems (ISCAS), 2014 IEEE International Symposium on

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 1 June 2014 through 7 June 2014

ER -

A unique and robust single slice FPGA identification generator

Abstract

Conference

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Projects

R1118ECI: Centre for Secure Information Technologies (CSIT)

Cite this