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Abstract
In this paper, a new field-programmable gate array (FPGA) identification generator circuit is introduced based on physically unclonable function (PUF) technology. The new identification generator is able to convert flip-flop delay path variations to unique n-bit digital identifiers (IDs), while requiring only a single slice per ID bit by using 1-bit ID cells formed as hard-macros. An exemplary 128-bit identification generator is implemented on ten Xilinx Spartan-6 FPGA devices. Experimental results show an uniqueness of 48.52%, and reliability of 92.41% over a 25°C to 70°C temperature range and 10% fluctuation in supply voltage
Original language | English |
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Title of host publication | Circuits and Systems (ISCAS), 2014 IEEE International Symposium on |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1223-1226 |
Number of pages | 4 |
ISBN (Print) | 9781479934317 |
DOIs | |
Publication status | Published - 01 Jun 2014 |
Event | IEEE International Symposium on Circuits and Systems - Melbourne, Australia Duration: 01 Jun 2014 → 07 Jun 2014 |
Conference
Conference | IEEE International Symposium on Circuits and Systems |
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Country/Territory | Australia |
City | Melbourne |
Period | 01/06/2014 → 07/06/2014 |
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Dive into the research topics of 'A unique and robust single slice FPGA identification generator'. Together they form a unique fingerprint.Projects
- 1 Finished
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R1118ECI: Centre for Secure Information Technologies (CSIT)
McCanny, J. V. (PI), Cowan, C. (CoI), Crookes, D. (CoI), Fusco, V. (CoI), Linton, D. (CoI), Liu, W. (CoI), Miller, P. (CoI), O'Neill, M. (CoI), Scanlon, W. (CoI) & Sezer, S. (CoI)
01/08/2009 → 30/06/2014
Project: Research