A VLSI architecture for multiplication, division and square root

S.E. McQuillan, J.V. McCanny

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

5 Citations (Scopus)

Abstract

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.
Original languageEnglish
Title of host publicationProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Pages1205-1208
Number of pages4
Volume2
Publication statusPublished - 01 Jan 1991

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