A VLSI architecture for multiplication, division and square root

S.E. McQuillan; J.V. McCanny

A VLSI architecture for multiplication, division and square root

Research output: Chapter in Book/Report/Conference proceeding › Other chapter contribution

Abstract

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

Original language	English
Title of host publication	Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Pages	1205-1208
Number of pages	4
Volume	2
Publication status	Published - 01 Jan 1991

Cite this

@inbook{4aeda043e5234a6ebbd17fe1803b193c,

title = "A VLSI architecture for multiplication, division and square root",

abstract = "A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.",

author = "S.E. McQuillan and J.V. McCanny",

year = "1991",

month = jan,

day = "1",

language = "English",

volume = "2",

pages = "1205--1208",

booktitle = "Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing",

}

TY - CHAP

T1 - A VLSI architecture for multiplication, division and square root

AU - McQuillan, S.E.

AU - McCanny, J.V.

PY - 1991/1/1

Y1 - 1991/1/1

N2 - A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

AB - A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

UR - http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-0026368492&md5=2730e205a6b08431bae72bd1a612296a

M3 - Other chapter contribution

AN - SCOPUS:0026368492

VL - 2

SP - 1205

EP - 1208

BT - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing

ER -

A VLSI architecture for multiplication, division and square root

Abstract

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