A VLSI architecture for variable block size video motion estimation

S.Y. Yap, John McCanny

Research output: Contribution to journalArticlepeer-review

153 Citations (Scopus)
387 Downloads (Pure)

Abstract

With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.
Original languageEnglish
Pages (from-to)384-389
Number of pages6
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume51
Issue number7
DOIs
Publication statusPublished - 19 Jul 2004

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

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