FPGAs can offer high performance with low power and low hardware usage. However, with current software, FPGA sare hard to program, and lengthy re-synthesis times make them unsuitable for the algorithm experimentation which is typical of developing image processing applications. In this paper, we present a system model based on a set of Soft Co-Processors, each of which implements a basic image-level operation (or a common combination of such operations) based on the high-level operators in Image Algebra. Both ‘debug’ (generic but unoptimised) and‘release’ (specific and optimised) versions of the SoftCo-Processors can be used. The advantage of debug mode is that no re-synthesis is required during algorithm experimentation. For release mode, a novel macro-based transformation tool enablesthe creation of a set of reusable HLS skeleton co-processors which require the user only to write a C function to obtain a new,special-purpose Soft Co-Processor.Initial experiments with several algorithms show that the areaand speed overheads for using debug (rather than release) mode are both around 25-30%, thus enabling algorithm development to take place on the FPGA itself. For creating function-specific Co-processors using our macro-based tool, the overheads compared with an expert hardware design are around 20%.
|Publication status||Published - 23 Jun 2018|
|Event||29th Irish Signals and Systems Conference 2018 - |
Duration: 21 Jun 2018 → 22 Jun 2018
|Conference||29th Irish Signals and Systems Conference 2018|
|Period||21/06/2018 → 22/06/2018|
- image processing
- Image Algebra
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Electrical and Electronic Engineering
- Signal Processing
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Student thesis: Doctoral Thesis › Doctor of Philosophy