Acceptance and Commitment Therapy for late-life treatment-resistant generalised anxiety disorder: A feasibility study

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number
generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in
battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest
reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for
the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based
PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the
routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells
that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from
a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale
comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been
investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and minentropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that
the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between
devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are
slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower
than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing
memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data
for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or
validation.