TY - GEN
T1 - AI-based timing error modelling: a case study on a pipelined floating-point core
AU - Tompazi, Styliani
AU - Karakonstantis, Georgios
PY - 2024/3/19
Y1 - 2024/3/19
N2 - The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2]. Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5]. However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.
AB - The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2]. Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5]. However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.
U2 - 10.1109/ARITH58626.2023.00035
DO - 10.1109/ARITH58626.2023.00035
M3 - Conference contribution
AN - SCOPUS:85189342633
SN - 9798350319231
T3 - Proceedings - IEEE Symposium on Computer Arithmetic (ARITH)
SP - 110
BT - Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 30th IEEE Symposium on Computer Arithmetic, ARITH 2023
Y2 - 4 September 2023 through 6 September 2023
ER -