AI-based timing error modelling: a case study on a pipelined floating-point core

Styliani Tompazi; Georgios Karakonstantis

doi:10.1109/ARITH58626.2023.00035

AI-based timing error modelling: a case study on a pipelined floating-point core

Styliani Tompazi^*
, Georgios Karakonstantis

^*Corresponding author for this work

Institute of Electronics, Communications & Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2]. Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5]. However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.

Original language	English
Title of host publication	Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	110
Number of pages	1
ISBN (Electronic)	9798350319224
ISBN (Print)	9798350319231
DOIs	https://doi.org/10.1109/ARITH58626.2023.00035
Publication status	Published - 19 Mar 2024
Event	30th IEEE Symposium on Computer Arithmetic, ARITH 2023 - Portland, United States Duration: 04 Sept 2023 → 06 Sept 2023

Publication series

Name	Proceedings - IEEE Symposium on Computer Arithmetic (ARITH)
ISSN (Print)	1063-6889
ISSN (Electronic)	2576-2265

Conference

Conference	30th IEEE Symposium on Computer Arithmetic, ARITH 2023
Country/Territory	United States
City	Portland
Period	04/09/2023 → 06/09/2023

ASJC Scopus subject areas

Software
Theoretical Computer Science
Hardware and Architecture

Access to Document

10.1109/ARITH58626.2023.00035Licence: Unspecified

Microarchitecture and workload-aware error prediction based on artificial intelligence
Tompazi, S. (Author), Karakonstantis, G. (Supervisor) & Martinez del Rincon, J. (Supervisor), Jul 2025
Student thesis: Doctoral Thesis › Doctor of Philosophy

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Tompazi, S., & Karakonstantis, G. (2024). AI-based timing error modelling: a case study on a pipelined floating-point core. In Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023 (pp. 110). (Proceedings - IEEE Symposium on Computer Arithmetic (ARITH)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ARITH58626.2023.00035

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title = "AI-based timing error modelling: a case study on a pipelined floating-point core",

abstract = "The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2]. Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5]. However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.",

author = "Styliani Tompazi and Georgios Karakonstantis",

year = "2024",

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day = "19",

doi = "10.1109/ARITH58626.2023.00035",

language = "English",

isbn = "9798350319231",

series = "Proceedings - IEEE Symposium on Computer Arithmetic (ARITH)",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "110",

booktitle = "Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023",

address = "United States",

note = "30th IEEE Symposium on Computer Arithmetic, ARITH 2023 ; Conference date: 04-09-2023 Through 06-09-2023",

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Tompazi, S & Karakonstantis, G 2024, AI-based timing error modelling: a case study on a pipelined floating-point core. in Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023. Proceedings - IEEE Symposium on Computer Arithmetic (ARITH), Institute of Electrical and Electronics Engineers Inc., pp. 110, 30th IEEE Symposium on Computer Arithmetic, ARITH 2023, Portland, United States, 04/09/2023. https://doi.org/10.1109/ARITH58626.2023.00035

AI-based timing error modelling: a case study on a pipelined floating-point core. / Tompazi, Styliani; Karakonstantis, Georgios.
Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023. Institute of Electrical and Electronics Engineers Inc., 2024. p. 110 (Proceedings - IEEE Symposium on Computer Arithmetic (ARITH)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - AI-based timing error modelling: a case study on a pipelined floating-point core

AU - Tompazi, Styliani

AU - Karakonstantis, Georgios

PY - 2024/3/19

Y1 - 2024/3/19

N2 - The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2]. Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5]. However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.

AB - The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2]. Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5]. However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.

U2 - 10.1109/ARITH58626.2023.00035

DO - 10.1109/ARITH58626.2023.00035

M3 - Conference contribution

AN - SCOPUS:85189342633

SN - 9798350319231

T3 - Proceedings - IEEE Symposium on Computer Arithmetic (ARITH)

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BT - Proceedings - 2023 IEEE 30th Symposium on Computer Arithmetic, ARITH 2023

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T2 - 30th IEEE Symposium on Computer Arithmetic, ARITH 2023

Y2 - 4 September 2023 through 6 September 2023

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AI-based timing error modelling: a case study on a pipelined floating-point core

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

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Student theses

Microarchitecture and workload-aware error prediction based on artificial intelligence

Cite this