An area aware accelerator for elliptic curve point multiplication

Malik Imran; Samuel Pagliarini; Muhammad Rashid

doi:10.1109/ICECS49266.2020.9294908

An area aware accelerator for elliptic curve point multiplication

Malik Imran
, Samuel Pagliarini
, Muhammad Rashid

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.

Original language	English
Title of host publication	ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	4
ISBN (Electronic)	9781728160443
DOIs	https://doi.org/10.1109/ICECS49266.2020.9294908
Publication status	Published - 28 Dec 2020
Externally published	Yes
Event	27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020 - Glasgow, United Kingdom Duration: 23 Nov 2020 → 25 Nov 2020

Publication series

Name	ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

Conference

Conference	27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020
Country/Territory	United Kingdom
City	Glasgow
Period	23/11/2020 → 25/11/2020

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

ASIC
Elliptic curve cryptography
FPGA
Montgomery algorithm
Point multiplication

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS49266.2020.9294908Licence: Unspecified

Cite this

Imran, M., Pagliarini, S., & Rashid, M. (2020). An area aware accelerator for elliptic curve point multiplication. In ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings Article 9294908 (ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS49266.2020.9294908

Imran, Malik ; Pagliarini, Samuel ; Rashid, Muhammad. / An area aware accelerator for elliptic curve point multiplication. ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings).

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title = "An area aware accelerator for elliptic curve point multiplication",

abstract = "This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.",

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author = "Malik Imran and Samuel Pagliarini and Muhammad Rashid",

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year = "2020",

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doi = "10.1109/ICECS49266.2020.9294908",

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series = "ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings",

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Imran, M, Pagliarini, S & Rashid, M 2020, An area aware accelerator for elliptic curve point multiplication. in ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings., 9294908, ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings, Institute of Electrical and Electronics Engineers Inc., 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, United Kingdom, 23/11/2020. https://doi.org/10.1109/ICECS49266.2020.9294908

An area aware accelerator for elliptic curve point multiplication. / Imran, Malik; Pagliarini, Samuel; Rashid, Muhammad.
ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9294908 (ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An area aware accelerator for elliptic curve point multiplication

AU - Imran, Malik

AU - Pagliarini, Samuel

AU - Rashid, Muhammad

PY - 2020/12/28

Y1 - 2020/12/28

N2 - This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.

AB - This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.

KW - ASIC

KW - Elliptic curve cryptography

KW - FPGA

KW - Montgomery algorithm

KW - Point multiplication

U2 - 10.1109/ICECS49266.2020.9294908

DO - 10.1109/ICECS49266.2020.9294908

M3 - Conference contribution

AN - SCOPUS:85099441664

T3 - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

BT - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020

Y2 - 23 November 2020 through 25 November 2020

ER -

Imran M, Pagliarini S, Rashid M. An area aware accelerator for elliptic curve point multiplication. In ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9294908. (ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings). doi: 10.1109/ICECS49266.2020.9294908

An area aware accelerator for elliptic curve point multiplication

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this