An investigation on inherent robustness of posit data representation

Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)
16 Downloads (Pure)

Abstract

As the dimensions and operating voltages of computer electronics shrink to cope with consumers' demand for higher performance and lower power consumption, circuit sensitivity to soft errors increases dramatically. Recently, a new data-type is proposed in the literature called posit data type. Posit arithmetic has absolute advantages such as higher numerical accuracy, speed, and simpler hardware design than IEEE 754-2008 technical standard-compliant arithmetic. In this paper, we propose a comparative robustness study between 32-bit posit and 32-bit IEEE 754-2008 compliant representations. At first, we propose a theoretical analysis for IEEE 754 compliant numbers and posit numbers for single bit flip and double bit flips. Then, we conduct exhaustive fault injection experiments that show a considerable inherent resilience in posit format compared to classical IEEE 754 compliant representation. To show a relevant use-case of fault-tolerant applications, we perform experiments on a set of machine-learning applications. In more than 95% of the exhaustive fault injection exploration, posit representation is less impacted by faults than the IEEE 754 compliant floating-point representation. Moreover, in 100% of the tested machine-learning applications, the accuracy of posit-implemented systems is higher than the classical floating-point-based ones.

Original languageEnglish
Title of host publicationProceedings of the 34th International Conference on VLSI Design and the 20th International Conference on Embedded Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages276-281
Number of pages6
ISBN (Electronic)9781665440875
ISBN (Print)9781665431279
DOIs
Publication statusPublished - 26 Apr 2021
Externally publishedYes
Event34th International Conference on VLSI Design and 20th International Conference on Embedded Systems - virtual, online, India
Duration: 20 Feb 202124 Feb 2021
https://doi.org/10.1109/VLSID51830.2021

Publication series

NameInternational Conference on VLSI Design: Proceedings
PublisherIEEE
ISSN (Print)1063-9667
ISSN (Electronic)2380-6923

Conference

Conference34th International Conference on VLSI Design and 20th International Conference on Embedded Systems
Abbreviated titleVLSID
Country/TerritoryIndia
Cityvirtual, online
Period20/02/202124/02/2021
Internet address

Keywords

  • Computer Arithmetic
  • Machine Learning
  • Posit Arithmetic
  • Reliability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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