Abstract
In this paper, we propose a novel finite impulse response (FIR) filter design methodology that reduces the number of operations with a motivation to reduce power consumption and enhance performance. The novelty of our approach lies in the generation of filter coefficients such that they conform to a given low-power architecture, while meeting the given filter specifications. The proposed algorithm is formulated as a mixed integer linear programming problem that minimizes chebychev error and synthesizes coefficients which consist of pre-specified alphabets. The new modified coefficients can be used for low-power VLSI implementation of vector scaling operations such as FIR filtering using computation sharing multiplier (CSHM). Simulations in 0.25um technology show that CSHM FIR filter architecture can result in 55% power and 34% speed improvement compared to carry save multiplier (CSAM) based filters.
Original language | English |
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Title of host publication | 2007 IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol II, Pts 1-3 |
Place of Publication | NEW YORK |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 49-52 |
Number of pages | 4 |
ISBN (Print) | ***************** |
Publication status | Published - 2007 |
Event | IEEE International Conference on Acoustics, Speech, and Signal Processing 2007 - Honolulu, United States Duration: 15 Apr 2007 → 20 Apr 2007 https://doi.org/10.1109/ICASSP10710.2007 |
Publication series
Name | International Conference on Acoustics Speech and Signal Processing (ICASSP) |
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Publisher | IEEE |
ISSN (Print) | 1520-6149 |
Conference
Conference | IEEE International Conference on Acoustics, Speech, and Signal Processing 2007 |
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Abbreviated title | ICASSP 2007 |
Country/Territory | United States |
City | Honolulu |
Period | 15/04/2007 → 20/04/2007 |
Internet address |
Keywords
- multiplierless digital filter design
- low power
- chebychev criterion
- optimization methods