Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.
ASJC Scopus subject areas
- Electrical and Electronic Engineering