Analysis and Design of a High-Efficiency Class-EM Power Amplifier

Moise Safari Mugisho; Mury Thian; Andrei Grebennikov

Analysis and Design of a High-Efficiency Class-EM Power Amplifier

Moise Safari Mugisho, Mury Thian, Andrei Grebennikov

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

121 Downloads (Pure)

Abstract

The Class-E M power amplifier (PA) offers the possibility of achieving high-efficiency operations at high operating frequencies while using slow-switching transistors. This is made possible by the adoption of the ZVS/ZVDS/ZCS and ZCDS conditions on the main circuit and the adoption of the ZVS condition on the auxiliary circuit. In this paper, we present the analysis and design of a new topology of the Class-E M PA incorporating a finite DC-feed inductance and an isolation circuit, rendering it more attractive for implementations. Furthermore, we propose a novel transmission-line load network that provides the drain of the transistor with the required load impedances at the fundamental frequency as well as at even and odd harmonic frequencies for the main and the auxiliary circuits. The concept is verified through harmonic-balance simulations with the PA exhibiting a peak drain efficiency of 90.3%, a peak power added efficiency of 86.7%, and a peak output power of 41.2 dBm at an operating frequency of 1.5 GHz.

Original language	English
Title of host publication	2019 IEEE Radio and Wireless Symposium (RWS)
Number of pages	4
ISBN (Electronic)	978-1-5386-5944-1
Publication status	Published - 16 May 2019

Publication series

Name	IEEE
ISSN (Print)	2164-2958
ISSN (Electronic)	2164-2974

Access to Document

Analysis and Design of a High-Efficiency Class-EM Power Amplifier
© 2018 IEEE. This work is made available online in accordance with the publisher’s policies. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 980 KBLicence: Unspecified

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Cite this

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title = "Analysis and Design of a High-Efficiency Class-EM Power Amplifier",

abstract = "The Class-E M power amplifier (PA) offers the possibility of achieving high-efficiency operations at high operating frequencies while using slow-switching transistors. This is made possible by the adoption of the ZVS/ZVDS/ZCS and ZCDS conditions on the main circuit and the adoption of the ZVS condition on the auxiliary circuit. In this paper, we present the analysis and design of a new topology of the Class-E M PA incorporating a finite DC-feed inductance and an isolation circuit, rendering it more attractive for implementations. Furthermore, we propose a novel transmission-line load network that provides the drain of the transistor with the required load impedances at the fundamental frequency as well as at even and odd harmonic frequencies for the main and the auxiliary circuits. The concept is verified through harmonic-balance simulations with the PA exhibiting a peak drain efficiency of 90.3%, a peak power added efficiency of 86.7%, and a peak output power of 41.2 dBm at an operating frequency of 1.5 GHz.",

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AU - Safari Mugisho, Moise

AU - Thian, Mury

AU - Grebennikov, Andrei

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N2 - The Class-E M power amplifier (PA) offers the possibility of achieving high-efficiency operations at high operating frequencies while using slow-switching transistors. This is made possible by the adoption of the ZVS/ZVDS/ZCS and ZCDS conditions on the main circuit and the adoption of the ZVS condition on the auxiliary circuit. In this paper, we present the analysis and design of a new topology of the Class-E M PA incorporating a finite DC-feed inductance and an isolation circuit, rendering it more attractive for implementations. Furthermore, we propose a novel transmission-line load network that provides the drain of the transistor with the required load impedances at the fundamental frequency as well as at even and odd harmonic frequencies for the main and the auxiliary circuits. The concept is verified through harmonic-balance simulations with the PA exhibiting a peak drain efficiency of 90.3%, a peak power added efficiency of 86.7%, and a peak output power of 41.2 dBm at an operating frequency of 1.5 GHz.

AB - The Class-E M power amplifier (PA) offers the possibility of achieving high-efficiency operations at high operating frequencies while using slow-switching transistors. This is made possible by the adoption of the ZVS/ZVDS/ZCS and ZCDS conditions on the main circuit and the adoption of the ZVS condition on the auxiliary circuit. In this paper, we present the analysis and design of a new topology of the Class-E M PA incorporating a finite DC-feed inductance and an isolation circuit, rendering it more attractive for implementations. Furthermore, we propose a novel transmission-line load network that provides the drain of the transistor with the required load impedances at the fundamental frequency as well as at even and odd harmonic frequencies for the main and the auxiliary circuits. The concept is verified through harmonic-balance simulations with the PA exhibiting a peak drain efficiency of 90.3%, a peak power added efficiency of 86.7%, and a peak output power of 41.2 dBm at an operating frequency of 1.5 GHz.

M3 - Conference contribution

T3 - IEEE

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