Abstract
This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series. The design exploits distributed arithmetic, parallelism, and pipelining to achieve a high-performance custom-computing implementation.
Original language | English |
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Pages (from-to) | 30-38 |
Number of pages | 9 |
Journal | IEEE DESIGN & TEST OF COMPUTERS |
Volume | 15 |
Issue number | 1 |
Publication status | Published - Jan 1998 |
ASJC Scopus subject areas
- Hardware and Architecture