Architectural review of polynomial bases finite field multipliers over GF(2m)

Malik Imran; Muhammad Rashid

doi:10.1109/C-CODE.2017.7918952

Architectural review of polynomial bases finite field multipliers over GF(2^m)

Malik Imran, Muhammad Rashid

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

36 Citations (Scopus)

Abstract

In elliptic curve cryptography (ECC), hardware architectures of finite field (FF) multipliers are frequently proposed for polynomial as well as for normal bases representations over GF(2^m). Although the polynomial bases provide efficient FF multiplication as compared to normal bases, the performance of the entire elliptic cryptosystem mainly depends upon its FF multiplier. Consequently, this paper provides a comparative overview of the recent hardware architectures of FF multipliers for polynomial bases over GF(2^m). This is achieved by classifying the most recent state-of-the-art research practices into three categories: Bit-serial, bit-parallel and digit-serial multipliers. The comparison of multiple techniques in this article enables the designer to select a suitable multiplier according to different application requirements such as high speed/performance, constrained environments and high throughput/area applications.

Original language	English
Title of host publication	Proceedings of 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	331-336
Number of pages	6
ISBN (Electronic)	9781509044481
DOIs	https://doi.org/10.1109/C-CODE.2017.7918952
Publication status	Published - 04 May 2017
Externally published	Yes
Event	2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017 - Islamabad, Pakistan Duration: 08 Mar 2017 → 09 Mar 2017

Publication series

Name	Proceedings of the International Conference on Communication, Computing and Digital Systems (C-CODE)
Publisher	IEEE

Conference

Conference	2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017
Country/Territory	Pakistan
City	Islamabad
Period	08/03/2017 → 09/03/2017

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

bit-parallel
bit-serial
digit serial
finite field multipliers
hardware architectures
Polynomial bases

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Computer Vision and Pattern Recognition
Signal Processing

Access to Document

10.1109/C-CODE.2017.7918952Licence: Unspecified

Cite this

Imran, M., & Rashid, M. (2017). Architectural review of polynomial bases finite field multipliers over GF(2^m). In Proceedings of 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017 (pp. 331-336). Article 7918952 (Proceedings of the International Conference on Communication, Computing and Digital Systems (C-CODE)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/C-CODE.2017.7918952

Imran, Malik ; Rashid, Muhammad. / Architectural review of polynomial bases finite field multipliers over GF(2^m). Proceedings of 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 331-336 (Proceedings of the International Conference on Communication, Computing and Digital Systems (C-CODE)).

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abstract = "In elliptic curve cryptography (ECC), hardware architectures of finite field (FF) multipliers are frequently proposed for polynomial as well as for normal bases representations over GF(2m). Although the polynomial bases provide efficient FF multiplication as compared to normal bases, the performance of the entire elliptic cryptosystem mainly depends upon its FF multiplier. Consequently, this paper provides a comparative overview of the recent hardware architectures of FF multipliers for polynomial bases over GF(2m). This is achieved by classifying the most recent state-of-the-art research practices into three categories: Bit-serial, bit-parallel and digit-serial multipliers. The comparison of multiple techniques in this article enables the designer to select a suitable multiplier according to different application requirements such as high speed/performance, constrained environments and high throughput/area applications.",

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Imran, M & Rashid, M 2017, Architectural review of polynomial bases finite field multipliers over GF(2^m). in Proceedings of 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017., 7918952, Proceedings of the International Conference on Communication, Computing and Digital Systems (C-CODE), Institute of Electrical and Electronics Engineers Inc., pp. 331-336, 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017, Islamabad, Pakistan, 08/03/2017. https://doi.org/10.1109/C-CODE.2017.7918952

Architectural review of polynomial bases finite field multipliers over GF(2^m). / Imran, Malik; Rashid, Muhammad.
Proceedings of 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 331-336 7918952 (Proceedings of the International Conference on Communication, Computing and Digital Systems (C-CODE)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - In elliptic curve cryptography (ECC), hardware architectures of finite field (FF) multipliers are frequently proposed for polynomial as well as for normal bases representations over GF(2m). Although the polynomial bases provide efficient FF multiplication as compared to normal bases, the performance of the entire elliptic cryptosystem mainly depends upon its FF multiplier. Consequently, this paper provides a comparative overview of the recent hardware architectures of FF multipliers for polynomial bases over GF(2m). This is achieved by classifying the most recent state-of-the-art research practices into three categories: Bit-serial, bit-parallel and digit-serial multipliers. The comparison of multiple techniques in this article enables the designer to select a suitable multiplier according to different application requirements such as high speed/performance, constrained environments and high throughput/area applications.

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Imran M, Rashid M. Architectural review of polynomial bases finite field multipliers over GF(2^m). In Proceedings of 2017 International Conference on Communication, Computing and Digital Systems, C-CODE 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 331-336. 7918952. (Proceedings of the International Conference on Communication, Computing and Digital Systems (C-CODE)). doi: 10.1109/C-CODE.2017.7918952