Architectural synthesis and efficient circuit implementation for field programmable gate arrays

D. W. Trainor, R. F. Woods

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The concept of “systems on silicon” has generated great interest in system-level synthesis and associated design tools. However, the challenges of a complete automated design flow for FPGAs, allowing algorithmic exploration, architectural design and efficient implementation have not yet been met. In order to meet these challenges, the IRIS synthesis system has been developed, and this paper describes the methodology and capabilities of IRIS, and demonstrates how this tool can apply automated system-level synthesis to derive FPGA designs, and also ensure that the hardware on the device is used very efficiently at the implementation stage.

Original languageEnglish
Title of host publicationField-Programmable Logic
Subtitle of host publicationSmart Applications, New Paradigms and Compilers - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996, Proceedings
EditorsManfred Glesner, Reiner W. Hartenstein
PublisherSpringer-Verlag
Pages116-125
Number of pages10
ISBN (Print)9783540617303
Publication statusPublished - 01 Jan 1996
Event6th International Workshop on Field-Programmable Logic and Applications, FPL 1996 - Darmstadt, Germany
Duration: 23 Sep 199625 Sep 1996

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1142
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference6th International Workshop on Field-Programmable Logic and Applications, FPL 1996
CountryGermany
CityDarmstadt
Period23/09/199625/09/1996

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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  • Cite this

    Trainor, D. W., & Woods, R. F. (1996). Architectural synthesis and efficient circuit implementation for field programmable gate arrays. In M. Glesner, & R. W. Hartenstein (Eds.), Field-Programmable Logic: Smart Applications, New Paradigms and Compilers - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996, Proceedings (pp. 116-125). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1142). Springer-Verlag.