TY - GEN
T1 - Architectural synthesis and efficient circuit implementation for field programmable gate arrays
AU - Trainor, D. W.
AU - Woods, R. F.
PY - 1996/1/1
Y1 - 1996/1/1
N2 - The concept of “systems on silicon” has generated great interest in system-level synthesis and associated design tools. However, the challenges of a complete automated design flow for FPGAs, allowing algorithmic exploration, architectural design and efficient implementation have not yet been met. In order to meet these challenges, the IRIS synthesis system has been developed, and this paper describes the methodology and capabilities of IRIS, and demonstrates how this tool can apply automated system-level synthesis to derive FPGA designs, and also ensure that the hardware on the device is used very efficiently at the implementation stage.
AB - The concept of “systems on silicon” has generated great interest in system-level synthesis and associated design tools. However, the challenges of a complete automated design flow for FPGAs, allowing algorithmic exploration, architectural design and efficient implementation have not yet been met. In order to meet these challenges, the IRIS synthesis system has been developed, and this paper describes the methodology and capabilities of IRIS, and demonstrates how this tool can apply automated system-level synthesis to derive FPGA designs, and also ensure that the hardware on the device is used very efficiently at the implementation stage.
UR - http://www.scopus.com/inward/record.url?scp=84955609891&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84955609891
SN - 9783540617303
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 116
EP - 125
BT - Field-Programmable Logic
A2 - Glesner, Manfred
A2 - Hartenstein, Reiner W.
PB - Springer-Verlag
T2 - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996
Y2 - 23 September 1996 through 25 September 1996
ER -