Architectural synthesis of an image processing algorithm using IRIS

D.W. Trainor; R.F. Woods; J.V. McCanny

Architectural synthesis of an image processing algorithm using IRIS

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Details are presented of the IRIS synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit.

Original language	English
Title of host publication	IEEE VLSI Signal Processing VIII, IEEE Signal Processing Soc. ed. T Nishitani, K Pahri
Pages	167-176
Number of pages	10
Publication status	Published - 01 Jan 1995

Bibliographical note

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title = "Architectural synthesis of an image processing algorithm using IRIS",

abstract = "Details are presented of the IRIS synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit.",

author = "D.W. Trainor and R.F. Woods and J.V. McCanny",

year = "1995",

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AU - Woods, R.F.

AU - McCanny, J.V.

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N2 - Details are presented of the IRIS synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit.

AB - Details are presented of the IRIS synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. The applicability of the system is demonstrated using the design example of a one-dimensional Discrete Cosine Transform circuit.

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M3 - Conference contribution

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BT - IEEE VLSI Signal Processing VIII, IEEE Signal Processing Soc. ed. T Nishitani, K Pahri

ER -

Architectural synthesis of an image processing algorithm using IRIS

Abstract

Bibliographical note

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