Area-delay-power-aware adder placement method for RNS reverse converter design

Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa; Mehdi  Hosseinzadeh; Keivan Navi

doi:10.1109/LASCAS.2016.7451050

Area-delay-power-aware adder placement method for RNS reverse converter design

Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini^*, Leonel Sousa, Mehdi Hosseinzadeh, Keivan Navi

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.

Original language	English
Title of host publication	2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	223-226
ISBN (Electronic)	9781467378352
DOIs	https://doi.org/10.1109/LASCAS.2016.7451050
Publication status	Published - 14 Apr 2016
Externally published	Yes
Event	2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) - Florianopolis, Brazil Duration: 28 Feb 2016 → 02 Mar 2016

Conference

Conference	2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)
Country/Territory	Brazil
City	Florianopolis
Period	28/02/2016 → 02/03/2016

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Emrani Zarandi, A. A., Sabbagh Molahosseini, A., Sousa, L., Hosseinzadeh, M., & Navi, K. (2016). Area-delay-power-aware adder placement method for RNS reverse converter design. In 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): proceedings (pp. 223-226). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS.2016.7451050

@inproceedings{9612d58b1f604a8d8541318335f87130,

title = "Area-delay-power-aware adder placement method for RNS reverse converter design",

abstract = "Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.",

author = "{Emrani Zarandi}, {Azadeh Alsadat} and {Sabbagh Molahosseini}, Amir and Leonel Sousa and Mehdi Hosseinzadeh and Keivan Navi",

year = "2016",

month = apr,

day = "14",

doi = "10.1109/LASCAS.2016.7451050",

language = "English",

pages = "223--226",

booktitle = "2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) ; Conference date: 28-02-2016 Through 02-03-2016",

}

Emrani Zarandi, AA , Sabbagh Molahosseini, A, Sousa, L, Hosseinzadeh, M & Navi, K 2016, Area-delay-power-aware adder placement method for RNS reverse converter design. in 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): proceedings. Institute of Electrical and Electronics Engineers Inc., pp. 223-226, 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), Florianopolis, Brazil, 28/02/2016. https://doi.org/10.1109/LASCAS.2016.7451050

Area-delay-power-aware adder placement method for RNS reverse converter design. / Emrani Zarandi, Azadeh Alsadat ; Sabbagh Molahosseini, Amir; Sousa, Leonel et al.
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. p. 223-226.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Area-delay-power-aware adder placement method for RNS reverse converter design

AU - Emrani Zarandi, Azadeh Alsadat

AU - Sabbagh Molahosseini, Amir

AU - Sousa, Leonel

AU - Hosseinzadeh, Mehdi

AU - Navi, Keivan

PY - 2016/4/14

Y1 - 2016/4/14

N2 - Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.

AB - Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.

U2 - 10.1109/LASCAS.2016.7451050

DO - 10.1109/LASCAS.2016.7451050

M3 - Conference contribution

SP - 223

EP - 226

BT - 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)

Y2 - 28 February 2016 through 2 March 2016

ER -

Area-delay-power-aware adder placement method for RNS reverse converter design

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