Area-efficient high-speed 3D DWT processor architecture

M. Jiang, Daniel Crookes

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)


An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.
Original languageEnglish
Pages (from-to)502-503
Number of pages2
JournalElectronics Letters
Issue number9
Publication statusPublished - 2007

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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