Area-efficient high-speed 3D DWT processor architecture

M. Jiang; Daniel Crookes

doi:10.1049/el:20070201

Area-efficient high-speed 3D DWT processor architecture

M. Jiang
, Daniel Crookes

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

Original language	English
Pages (from-to)	502-503
Number of pages	2
Journal	Electronics Letters
Volume	43
Issue number	9
DOIs	https://doi.org/10.1049/el:20070201
Publication status	Published - 2007

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:20070201

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AB - An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

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Area-efficient high-speed 3D DWT processor architecture

Abstract

ASJC Scopus subject areas

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