Bit-level systolic architecture for very high performance IIR filters

Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny

Research output: Contribution to journalArticlepeer-review


A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.
Original languageEnglish
Pages (from-to)2449-2452
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication statusPublished - 01 Jan 1989

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.


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