Bit-Level systolic architectures for high performance IIR filtering

S.C. Knowles, J.G. McWhirter, R.F. Woods, J.V. McCanny

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)


Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware.
Original languageEnglish
Pages (from-to)9-24
Number of pages16
JournalJournal of VLSI signal processing systems for signal, image and video technology
Issue number1
Publication statusPublished - 01 Aug 1990

Bibliographical note

Copyright 2007 Elsevier B.V., All rights reserved.


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