Bit-level systolic array implementation of the Winograd Fourier transform algorithm

J.S. Ward, J.V. McCanny, J.G. McWhirter

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


A bit level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest-neighbor interconnections, regularity and high throughput. The short interconnections in this method contrast favorably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform a short length transform. These components build into longer transforms preserving the regularity and structure of the short length transform design.
Original languageEnglish
Pages (from-to)473-479
Number of pages7
JournalIEE Proceedings, Part F: Communications, Radar and Signal Processing
Issue number6
Publication statusPublished - 01 Oct 1985

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.


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