BIT-LEVEL SYSTOLIC ARRAYS.

J.V. McCanny, R.A. Evans

Research output: Contribution to journalArticlepeer-review

Abstract

A systolic array is an array of individual processing cells each of which has some local memory and is connected only to its nearest neighbours in the form of a regular lattice. On each cycle of a simple clock every cell receives data from its neighbouring cells and performs a specific processing operation on it. The resulting data is stored within the cell and passed on to neighbouring cells on the next clock cycle. This paper gives an overview of work to date and illustrates the application of bit-level systolic arrays by means of two examples: (1) a pipelined bit-slice circuit for computing matrix x vector transforms; and (2) a bit serial structure for multi-bit convolution.
Original languageEnglish
JournalIEE Colloquium (Digest)
Issue number1984 /14
Publication statusPublished - 01 Jan 1984

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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